Mineeva, Tatyana A
2017-03-29 15:54:22 UTC
Hello Julian and Valgrind developers,
I'm working with the Intel team to add AVX-512 support to Valgrind.
Our team cannot access the Valgrind Subversion repository:
$ svn co svn://svn.valgrind.org/valgrind/trunk valgrind
svn: Can't connect to host 'svn.valgrind.org': Connection timed out
Is the this repository functional, or should we switch to the git repository?
We do not currently have success cloning the Valgrind git repository:
$ git clone git://sourceware.org/git/valgrind.git
Cloning into 'valgrind'...
fatal: unable to connect to sourceware.org:
sourceware.org[0: 209.132.180.131]: errno=Connection timed out
Might you or another developer have an idea of configuration settings we should use on our end?
I would also like to take this opportunity to update you on our current progress on adding AVX-512 support to Valgrind. We will appreciate any comments and questions.
We started with the base Valgrind 3.12.0 which we downloaded from the website.
- Extended Valgrind's HW capabilities detection to detect AVX-512 support and tell VEX about it.
- Extended the implementation of XSAVE and XRSTOR to cover the new registers. We tested it under Nulgrind on the tests from ./memcheck/tests/amd64/xsave-avx.c, which we extended to cover the new register state. We haven't yet tested it on a real context switch or runtime library call.
- Added support of a few AVX-512 instructions (vmovups, vmovdqa32, vmovdqa64, vpsubd) to Valgrind core. The instructions double up the IR of their AVX-2 version.
- For the tests, we are using a slightly modified version of none/tests/amd64/avx2-1.c. Basically, it replaces ymm registers with zmm registers; it does not verify the new features of AVX-512 instructions (such as opmasks) yet. The newly added instructions pass the tests under Nulgrind.
- We are currently adding support of the new registers to memcheck.
We plan to try implementing some AVX-512 instructions without doubling up the existing IR next.
Best regards,
Tanya
--------------------------------------------------------------------
Joint Stock Company Intel A/O
Registered legal address: Krylatsky Hills Business Park,
17 Krylatskaya Str., Bldg 4, Moscow 121614,
Russian Federation
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
I'm working with the Intel team to add AVX-512 support to Valgrind.
Our team cannot access the Valgrind Subversion repository:
$ svn co svn://svn.valgrind.org/valgrind/trunk valgrind
svn: Can't connect to host 'svn.valgrind.org': Connection timed out
Is the this repository functional, or should we switch to the git repository?
We do not currently have success cloning the Valgrind git repository:
$ git clone git://sourceware.org/git/valgrind.git
Cloning into 'valgrind'...
fatal: unable to connect to sourceware.org:
sourceware.org[0: 209.132.180.131]: errno=Connection timed out
Might you or another developer have an idea of configuration settings we should use on our end?
I would also like to take this opportunity to update you on our current progress on adding AVX-512 support to Valgrind. We will appreciate any comments and questions.
We started with the base Valgrind 3.12.0 which we downloaded from the website.
- Extended Valgrind's HW capabilities detection to detect AVX-512 support and tell VEX about it.
- Extended the implementation of XSAVE and XRSTOR to cover the new registers. We tested it under Nulgrind on the tests from ./memcheck/tests/amd64/xsave-avx.c, which we extended to cover the new register state. We haven't yet tested it on a real context switch or runtime library call.
- Added support of a few AVX-512 instructions (vmovups, vmovdqa32, vmovdqa64, vpsubd) to Valgrind core. The instructions double up the IR of their AVX-2 version.
- For the tests, we are using a slightly modified version of none/tests/amd64/avx2-1.c. Basically, it replaces ymm registers with zmm registers; it does not verify the new features of AVX-512 instructions (such as opmasks) yet. The newly added instructions pass the tests under Nulgrind.
- We are currently adding support of the new registers to memcheck.
We plan to try implementing some AVX-512 instructions without doubling up the existing IR next.
Best regards,
Tanya
--------------------------------------------------------------------
Joint Stock Company Intel A/O
Registered legal address: Krylatsky Hills Business Park,
17 Krylatskaya Str., Bldg 4, Moscow 121614,
Russian Federation
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.