SWIS on x86

[Camiel Vanderhoeven]

Since there’s been a fair amount of conversation lately about your wishes for more communications from us (VSI), I figured I could join in and share a bit with you about what I’m currently working on.

As some of you may know, I’m part of the x86 porting project, and I’m responsible for some very low-level (close to the hardware) aspects of the OS. For the past year-and-a-half, I’ve been working on the design for the SWIS (Software Interrupt Services) layer for X86; full-time for some months in the beginning and end, part-time for about a year while I was mostly focused on the Java 8 port with Brett.

For those who don’t know what SWIS is, it’s a piece of software that was designed as part of porting VMS to Itanium, that provides VAX- and Alpha-like mechanisms that are not natively available on the hardware to the rest of the operating system; it’s partly a replacement for the PALcode on Alpha, partly a replacement for hardware mechanisms built into Alpha. The main features it provides the rest of the OS with are 32 IPL levels, prioritization of hardware interrupts to the 16 high IPL levels, and software interrupts tied to the 16 low IPL levels, as well as ASTs for each of the four modes.

On x86, SWIS will be partly responsible for more VAX- and Alpha-like features, like the 4 modes we’re used to, each with their own page protections. (The X86 hardware provides us only with two useable rings).

A couple of weeks ago, shortly after completing a first draft of the SWIS design, I spent two weeks at the headquarters in Bolton (I'm based in the Netherlands, and usually work from home). During this two-week visit, I was fortunate to have Burns Fisher - Digital/Compaq/VSI alumnus and architect of the SWIS layer on Itanium - brought in as a consultant for several days. During those days, we went through the design with a very fine tooth comb. We did find a flaw in the design, one that would have made it possible for user-mode code to exhaust the kernel stack, bringing the system down with a kernel-stack invalid bug check, and we found a few places where more clarification was in order.

Following that, we organized a design review meeting with most of the X86 team, where we presented the finished design. I plan to offer a simplified version of that presentation at boot camp.

The design being reviewed and approved, I have began implementing the SWIS layer. The first item that has been implemented is a primitive exception handler that can be used at boot time; Paul Jacobi is working to give us debugging capabilities very early on in SYSBOOT that uses this primitive handler.

Further parts of the implementation will include emulation of VAX/Alpha-like internal processor registers (MFPR/MTPR instructions), full-fledged exception, interrupt and machine check handling, system service dispatching, software interrupts, ASTs, context switching and scheduling, and the bootstrapping and initialization of all of the above.

Let me know if you have any questions, and please be aware that if we don’t seem to be around here very often, it’s possibly because we’re very hard at work actually building something.

Kind regards,

Camiel Vanderhoeven

[Simon Clubley]

Since there?s been a fair amount of conversation lately about your wishes
for more communications from us (VSI), I figured I could join in and share
a bit with you about what I?m currently working on.

Thank you. This type of feedback is very useful, keeps us in touch
with what is going on, and lets us know that things are progressing.

On x86, SWIS will be partly responsible for more VAX- and Alpha-like
features, like the 4 modes we?re used to, each with their own page
protections. (The X86 hardware provides us only with two useable rings).

One of the concerns I have had since the beginning is the possible
performance hit from having to emulate some of the KESU modes in the
x86-64 environment.

Do you have a feeling for what this performance hit is likely to be
in practice ?

For example, what is likely to be the typical performance hit on a normal
user process -> RMS exec mode -> Kernel driver sequence when reading and
writing records ?

Also, is this KESU emulation something that could be directly applied
to (for example) ARM, or are there any x86-64 features you are using
to reduce the pain of emulating some of the 4 modes in hardware ?

I've asked these questions before but the answers were not yet
completely clear previously.

Thanks,

Simon.

[Camiel Vanderhoeven]

Post by Simon Clubley

Post by Camiel Vanderhoeven
On x86, SWIS will be partly responsible for more VAX- and Alpha-like
features, like the 4 modes we?re used to, each with their own page
protections. (The X86 hardware provides us only with two useable rings).

One of the concerns I have had since the beginning is the possible
performance hit from having to emulate some of the KESU modes in the
x86-64 environment.
Do you have a feeling for what this performance hit is likely to be
in practice ?
For example, what is likely to be the typical performance hit on a normal
user process -> RMS exec mode -> Kernel driver sequence when reading and
writing records ?

It's difficult to put a number on this; this is certainly a feature/performance tradeoff. How much of an impact on performance this has depends not only on the particular application, but also on how many processes are active on a system, and whether or not certain features are available on the processor. Going off the record - if there is such a thing on COV - I personally expect the impact of this to be minimal (probably < 1%) in most cases on modern hardware.

Performance impact is caused by:
- Code required on any mode change to change to a different address space. This is a very, very small impact.
- Additional page table structures taking up more memory, and putting a higher load on the processor's data cache. Small impact.
- Impact of invalidating the processor's translation look aside buffers (TLBs) on a mode change.

The latter of these three certainly has the largest impact on performance, but this can be partially mitigated on processors that implement PCID (process context identifiers); PCIDs are the equivalent of ASNs (address space numbers) on Alpha, or RIDs (region ids) on Itanium, and are normally used to help distinguish between different process' entries in the TLBs; on processors that offer them (for now that means Intel processors newer than 2013), we'll use this mechanism. On older processors, we'll unfortunately have to invalidate the entirety of the TLB on a mode change. On processors that do offer PCIDs, the number of PCIDs available (4096) allow for 1024 processes per processor to have entries in the TLB. This is more than on Alpha (256 I believe), but far less than on Itanium (16 million). The way this works on Itanium, is that if we've exhausted the number of available RIDs, we invalidate the entire TLBs, and start assigning RIDs from scratch again. I've put looking into possible optimizations to this algorithm on my post-first-boot to-do list.

Post by Simon Clubley
Also, is this KESU emulation something that could be directly applied
to (for example) ARM, or are there any x86-64 features you are using
to reduce the pain of emulating some of the 4 modes in hardware ?

It most likely could. ARM offers a mechanism similar to the ASN/RID/PCID, the ASID (address space identifier).

Camiel

[Simon Clubley]

Post by Camiel Vanderhoeven

Post by Simon Clubley
For example, what is likely to be the typical performance hit on a normal
user process -> RMS exec mode -> Kernel driver sequence when reading and
writing records ?

It's difficult to put a number on this; this is certainly a
feature/performance tradeoff. How much of an impact on performance this has
depends not only on the particular application, but also on how many processes
are active on a system, and whether or not certain features are available on
the processor. Going off the record - if there is such a thing on COV - I
personally expect the impact of this to be minimal (probably < 1%) in most
cases on modern hardware.
- Code required on any mode change to change to a different address space.
This is a very, very small impact.
- Additional page table structures taking up more memory, and putting a
higher load on the processor's data cache. Small impact.
- Impact of invalidating the processor's translation look aside buffers
(TLBs) on a mode change.

The cost of a full blown TLB invalidation is certainly the major concern
for me.

Post by Camiel Vanderhoeven
The latter of these three certainly has the largest impact on
performance, but this can be partially mitigated on processors that
implement PCID (process context identifiers); PCIDs are the equivalent of
ASNs (address space numbers) on Alpha, or RIDs (region ids) on Itanium, and
are normally used to help distinguish between different process' entries in
the TLBs; on processors that offer them (for now that means Intel
processors newer than 2013), we'll use this mechanism. On older processors,
we'll unfortunately have to invalidate the entirety of the TLB on a mode
change. On processors that do offer PCIDs, the number of PCIDs available
(4096) allow for 1024 processes per processor to have entries in the TLB.
This is more than on Alpha (256 I believe), but far less than on Itanium
(16 million). The way this works on Itanium, is that if we've exhausted the
number of available RIDs, we invalidate the entire TLBs, and start
assigning RIDs from scratch again. I've put looking into possible
optimizations to this algorithm on my post-first-boot to-do list.

Yes, I was made aware of the existence of the PCIDs during previous
discussions, but it wasn't completely clear previously if VMS on x86-64
was actually planning to use them.

Post by Camiel Vanderhoeven

Post by Simon Clubley
Also, is this KESU emulation something that could be directly applied
to (for example) ARM, or are there any x86-64 features you are using
to reduce the pain of emulating some of the 4 modes in hardware ?

Arrghh! In case anyone is confused, that sentence should end with
"emulating some of the 4 modes in _software_", not hardware. :-(

Post by Camiel Vanderhoeven
It most likely could. ARM offers a mechanism similar to the ASN/RID/PCID,
the ASID (address space identifier).

Interesting, thanks. That's functionality in the ARM MMU I have not
had to look for or otherwise research yet.

Thanks,

Simon.

[Camiel Vanderhoeven]

Post by Simon Clubley
Yes, I was made aware of the existence of the PCIDs during previous
discussions, but it wasn't completely clear previously if VMS on x86-64
was actually planning to use them.

On platforms where it is available, definitely. It'd be very foolish not to use them if we can, particularly because we can't use the global bit in our pagetables (which is how most OSes avoid invalidating system space mappings on a context switch), because our system space protection bits differ between the four modes.

Current thinking is that we'll provide two flavors of the SWIS routines in two different execlets; there will be a "performance" execlet that uses some newer CPU features to speed things up (PCIDs, XSAVES, RDGSBASE to name a few), and a "compatibility" execlet for processors that lack one or more of these features. Which flavor of the execlet will get loaded is determined at boot time.

[Jan-Erik Soderholm]

Post by Camiel Vanderhoeven

Post by Simon Clubley

Post by Camiel Vanderhoeven
On x86, SWIS will be partly responsible for more VAX- and Alpha-like
features, like the 4 modes we?re used to, each with their own page
protections. (The X86 hardware provides us only with two useable rings).

One of the concerns I have had since the beginning is the possible
performance hit from having to emulate some of the KESU modes in the
x86-64 environment.
Do you have a feeling for what this performance hit is likely to be
in practice ?
For example, what is likely to be the typical performance hit on a normal
user process -> RMS exec mode -> Kernel driver sequence when reading and
writing records ?

It's difficult to put a number on this; this is certainly a feature/performance tradeoff. How much of an impact on performance this has depends not only on the particular application, but also on how many processes are active on a system, and whether or not certain features are available on the processor. Going off the record - if there is such a thing on COV - I personally expect the impact of this to be minimal (probably < 1%) in most cases on modern hardware.
- Code required on any mode change to change to a different address space. This is a very, very small impact.
- Additional page table structures taking up more memory, and putting a higher load on the processor's data cache. Small impact.
- Impact of invalidating the processor's translation look aside buffers (TLBs) on a mode change.
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

Jan-Erik.

[Camiel Vanderhoeven]

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this feature either. Current AMD processors don't, for instance.

[Simon Clubley]

Post by Camiel Vanderhoeven

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this feature either. Current AMD processors don't, for instance.

Because of the performance implications, this does mean that when
benchmarking VMS on x86-64 (for example) it will need to be very clear
in some $ show command somewhere which SWIS version has been loaded.

In case this hasn't already been added to the work list, I would
request one of the $ show commands is enhanced to show exactly which
SWIS version has been loaded.

The purpose is to head off the VMS is slow/no it isn't/it's your hardware/
no it isn't/etc :-) discussion by being able to ask someone to run this
enhanced $ show command and for them to be able to easily post the results.

Thanks,

Simon.

[David Froble]

Post by Camiel Vanderhoeven

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this feature either. Current AMD processors don't, for instance.

Has anybody rattled AMD's chain about this feature?

[Camiel Vanderhoeven]

Post by Camiel Vanderhoeven

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this feature either. Current AMD processors don't, for instance.

At first glance, the new AMD EPYC datacenter processor (http://www.amd.com/en/products/epyc) does not support PCID's or the InVPCID instruction either.

[Stephen Hoffman]

Post by Camiel Vanderhoeven

Post by Camiel Vanderhoeven

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors
newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this
feature either. Current AMD processors don't, for instance.

At first glance, the new AMD EPYC datacenter processor
(http://www.amd.com/en/products/epyc) does not support PCID's or the
InVPCID instruction either.

Sacrilege : Whether having four modes provides a sufficient
justification for the added complexity, effort and configuration
restrictions, and for any associated performance degradation?

[Camiel Vanderhoeven]

Post by Stephen Hoffman
Sacrilege : Whether having four modes provides a sufficient
justification for the added complexity, effort and configuration
restrictions, and for any associated performance degradation?

I wouldn't call it sacrilege to ask a question like that. Whether or not we should compress VMS's 4 modes down into 2, or come up with a scheme to give us 4 modes on x86 was one of the central questions early on when we decided to do the port, and one that we spent a lot of time on. I believe you're putting "effort" on the wrong side of the equation though. IMHO, the effort of implementing 4 modes is a lot less than the effort of dumbing down the OS to only use two modes, and to me, the result of the latter is far preferable. I believe that the performance traded in return for this will be very minor, and I'm not sure what configuration restrictions you're talking about.

[Stephen Hoffman]

Post by Camiel Vanderhoeven

Post by Stephen Hoffman
Sacrilege : Whether having four modes provides a sufficient
justification for the added complexity, effort and configuration
restrictions, and for any associated performance degradation?

I wouldn't call it sacrilege to ask a question like that. Whether or
not we should compress VMS's 4 modes down into 2, or come up with a
scheme to give us 4 modes on x86 was one of the central questions early
on when we decided to do the port, and one that we spent a lot of time
on. I believe you're putting "effort" on the wrong side of the equation
though. IMHO, the effort of implementing 4 modes is a lot less than the
effort of dumbing down the OS to only use two modes, and to me, the
result of the latter is far preferable. I believe that the performance
traded in return for this will be very minor, and I'm not sure what
configuration restrictions you're talking about.

Dumbing down? Interesting choice of phrasing for removing a whole lot
of complexity and clutter from the design, and making the design much
more compatible with modern processor designs.

But certainly bringing the memory management system design toward
better direct compatibility is — as you quite correctly comment — a
larger effort than working around it via SWIS.

For those reading along at home, OpenVMS only really has two modes in
terms of system security, and all security on OpenVMS is based on
control of the memory management gates. User mode unprivileged, and
the other three modes are either effectively or directly privileged.
In terms of stability, yes, user-, supervisor- and (some)
executive-mode crashes are not supposed to take out the whole system.
The downside of the design is that you're all in one big address space,
and kernel errors can be an utter joy to track down. As folks that
recall the FP bug that once lurked in the NFS server will attest.
Changing that would certainly make the kernel rather less like OpenVMS,
though OpenVMS itself was once ported over to a non-monolithic kernel.

As for configuration restrictions, you're tied to INVPCID et al, and
will potentially have to work around that omission on other processors.
But what the resulting performance of both the design and any
necessary workaround for the lack of INVPCID might be, and whether
there are security implications when working with mixed-ownership-modes
memory references from application and system code, y'all will
undoubtedly be the first to know.

If the SWIS four-mode design works and if it sells well enough, run
with it. But don't blindly follow old assumptions and old designs.
Challenge them. Look around. Look at where you want the designs to
be in ten years, too.

[John Reagan]

Post by Camiel Vanderhoeven

Post by Camiel Vanderhoeven

Post by Jan-Erik Soderholm

Post by Camiel Vanderhoeven
on processors that offer them (for now that means Intel processors newer than 2013),...

How large is the "risk" that VMS will ever be used on any x86-64 system
with a processor from before 2013? VMS/X86-64 is not like VMS for Alpha
or VAX where there was a need to support old customers with old hardware.

I agree with that, however, not all newer processors support this feature either. Current AMD processors don't, for instance.

At first glance, the new AMD EPYC datacenter processor (http://www.amd.com/en/products/epyc) does not support PCID's or the InVPCID instruction either.

No, but I did note that EPYC (and Ryzen) did add several new ISA subsets (but not AVX512).

[Richard Maher]

SWIS Stuff

Thanks for the update!

Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?

Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

Also a big "Well done!" and "Keep Going!" to all the engineers who must
get discouraged and ask themselves a few difficult questions from time
to time about the merit of what they're doing. You WILL deliver, and it
WILL pay off!

[Camiel Vanderhoeven]

Post by Richard Maher
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?

I'd say so. We've been fairly confident from the beginning, it's just been a matter of working out the details.

Post by Richard Maher
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

I'm not sure what debacle that is, and I'm not entirely comfortable to referring to female colleagues as "chicks". That said, you're wrong. I'm a 39 year old husband and father of 3.

Camiel

[Ian Miller]

Post by Camiel Vanderhoeven

Post by Richard Maher
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?

I'd say so. We've been fairly confident from the beginning, it's just been a matter of working out the details.

Post by Richard Maher
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

I'm not sure what debacle that is, and I'm not entirely comfortable to referring to female colleagues as "chicks". That said, you're wrong. I'm a 39 year old husband and father of 3.
Camiel

39 :-O

[Richard Maher]

Post by Ian Miller
39 :-O

I see it but I don't believe it. Best VMS news story this year!

[Camiel Vanderhoeven]

Post by Richard Maher

Post by Ian Miller
39 :-O

I see it but I don't believe it. Best VMS news story this year!

If you manage to make it to the boot camp one of these years, let's get properly acquainted over a beer or so. You might be able to teach me some Australian vernacular, and I might introduce you to the wonders of learning a few basic facts by Googling for someone ;-)

[Richard Maher]

Post by Camiel Vanderhoeven

Post by Richard Maher

Post by Ian Miller
39 :-O

I see it but I don't believe it. Best VMS news story this year!

If you manage to make it to the boot camp one of these years, let's get properly acquainted over a beer or so. You might be able to teach me some Australian vernacular, and I might introduce you to the wonders of learning a few basic facts by Googling for someone ;-)

Sounds good!

[Bill Gunshannon]

Post by Camiel Vanderhoeven

Post by Richard Maher
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?

I'd say so. We've been fairly confident from the beginning, it's just been a matter of working out the details.

Post by Richard Maher
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

I'm not sure what debacle that is, and I'm not entirely comfortable to referring to female colleagues as "chicks". That said, you're wrong. I'm a 39 year old husband and father of 3.
Camiel

Sure hope Richard is self-employed cause if he's not he must spend an
awful lot of time being counseled in HR. :-)

bill

[Richard Maher]

Post by Bill Gunshannon
Sure hope Richard is self-employed cause if he's not he must spend an
awful lot of time being counseled in HR. :-)

Mate you've got no idea :-(

The things I do to keep paying school fees for those who walked out on me.

2 strikes, 2 formal counselings, a HR threat from parking, and some knob
wanting to take away a privilege that I don't even want.

Absolutely none of this for gender or LGBTI issues or diversity and
inclusivity. You know what it's like? Once they've got a CoC they can
stitch you up for breathing especially when your mouth's as big as mine.

But I use it against them, ask them if they've reached their arsehole
quota for diversity and inclusivity and there's a strange silence. That
cat-loving knob Hixie honestly suggested inclusivity and diversity were
rights for people who cannot change and my 52 years as an arsehole
didn't mean I couldn't change. The fucking nerve of some people! What
next? Put me in a re-education camp and pray the wanker away?

What is it with all these wankers and cats??? Any of you with a cat just
go and get fucked now! (Unless your name is Dr. Evil) No, just take
another pointless photo and stick it on faceplant next to the one of
your dinner!

Speaking of wankers, look at the last 4 posts on this thread: -
https://drive.google.com/drive/u/0/folders/0B7Rmd3Rn8_hDMmFqWjlHUG5OQzQ

If you look at same at https://github.com/w3c/ServiceWorker/issues/745
you'll see how the cat-mafia, purple-mafia, prick-mafia protect each other.

I've been banned from Rdb Listserver, W3C/IETF Github forums, Microsoft
Dev, Mozilla Bugzilla, WICG and a few others I can't remember. Honestly,
there are times when I start to think that it's me.

Post by Bill Gunshannon
bill

[Chris]

Post by Richard Maher
Mate you've got no idea :-(

It's never easy being an outsider, as you end up upsetting everyone,
especially those who look to find fault with others. "Valuing
differences", in this modern pc world, you must be joking. All I
can say is, speak your truth as you find it, as those who would
judge are not your friends and can be ignored.

However, it's the outsiders and mavericks who cause progress in the
world, not those sitting on the fence. Life is not for the faint
hearted :-)...

Chris

[Richard Maher]

Post by Chris

Post by Richard Maher
Mate you've got no idea :-(

It's never easy being an outsider, as you end up upsetting everyone,
especially those who look to find fault with others. "Valuing
differences", in this modern pc world, you must be joking. All I
can say is, speak your truth as you find it, as those who would
judge are not your friends and can be ignored.
However, it's the outsiders and mavericks who cause progress in the
world, not those sitting on the fence. Life is not for the faint
hearted :-)...
Chris

Weel I managed to get the GeoFence API killed, Firebase implemented
Topic-based subscriptions in javascript and I WILL get background
geolocation over the line!

I take "thought leadership" very seriously :-)

[Paul Sture]

Post by Bill Gunshannon

Post by Camiel Vanderhoeven

Post by Richard Maher
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?

I'd say so. We've been fairly confident from the beginning, it's just
been a matter of working out the details.

Post by Richard Maher
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

I'm not sure what debacle that is, and I'm not entirely comfortable
to referring to female colleagues as "chicks". That said, you're
wrong. I'm a 39 year old husband and father of 3.
Camiel

Sure hope Richard is self-employed cause if he's not he must spend an
awful lot of time being counseled in HR. :-)

Applying the principle of "an enemy of my enemy is my friend", Richard
has probably got many friends. :-)

[Richard Maher]

Post by Paul Sture
Applying the principle of "an enemy of my enemy is my friend", Richard
has probably got many friends. :-)

Or "judge someone by the caliber of their enemies and not their friends"
still means I'm rubbish :-)

[Kerry Main]

-----Original Message-----
Camiel Vanderhoeven via Info-vax
Sent: June 19, 2017 7:44 AM
Subject: Re: [Info-vax] SWIS on x86

Post by Richard Maher
Has everyone else been able to just proceed in the confidence that

you

Post by Richard Maher
would succeed and deliver a hardware abstraction compatible with

IA64?
I'd say so. We've been fairly confident from the beginning, it's just been
a matter of working out the details.

Post by Richard Maher
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".

I'm not sure what debacle that is, and I'm not entirely comfortable to
referring to female colleagues as "chicks". That said, you're wrong. I'm a
39 year old husband and father of 3.
Camiel

I deal with these types of name issues all the time ..

"Kerry" at hotel desk or anonymous messages are almost always translated to "Ms."

Btw, calling someone a "chick" here would result in quickly learning why there is an old saying "hell hath no fury like a woman scorned"

😊

Regards,

Kerry Main
Kerry dot main at starkgaming dot com

[Richard Maher]

Post by Kerry Main
I deal with these types of name issues all the time ..
"Kerry" at hotel desk or anonymous messages are almost always translated to "Ms."

All I can say is your parents must have all been big Johnny Cash fans!
"My name is Sue! Well how do - you - do?"

Post by Kerry Main
Btw, calling someone a "chick" here would result in quickly learning why there is an old saying "hell hath no fury like a woman scorned"

Well "chick" here has no adverse connotations outside of perhaps the
professional offense takers. I suppose in the US you have "gals" but in
Oz "chicks" is the feminine of "guys". Familiar non-diminutive gender
designated collective noun. Apparently it's not PC to call a mixed group
"hey guys" :-(

But after the "transphobic" accusation for proffering only a
gender-binary solution to the conundrum "If your Aunt had balls she'd be
you Uncle!" I give up.

[Jan-Erik Soderholm]

Post by Richard Maher

SWIS Stuff

Thanks for the update!
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right?

5 seconds using a picture seach on Google would had saved you *that*
debacle...

[Bob Gezelter]

Post by Richard Maher

SWIS Stuff

Thanks for the update!
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".
Also a big "Well done!" and "Keep Going!" to all the engineers who must
get discouraged and ask themselves a few difficult questions from time
to time about the merit of what they're doing. You WILL deliver, and it
WILL pay off!

Richard,

Camiel is not a "chick". (although I will admit not having checked his passport). His wife and children can confirm.

- Bob Gezelter, http://www.rlgsc.com

[David Turner]

Clair debacle???
What happened?

Post by Bob Gezelter

Post by Richard Maher

SWIS Stuff

Thanks for the update!
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".
Also a big "Well done!" and "Keep Going!" to all the engineers who must
get discouraged and ask themselves a few difficult questions from time
to time about the merit of what they're doing. You WILL deliver, and it
WILL pay off!

Richard,
Camiel is not a "chick". (although I will admit not having checked his passport). His wife and children can confirm.
- Bob Gezelter, http://www.rlgsc.com

[Simon Clubley]

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

Simon.

[Scott Dorsey]

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

On the internet, we are all of us beautiful 18-year-old girls.
--scott

[Simon Clubley]

Post by Scott Dorsey

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

On the internet, we are all of us beautiful 18-year-old girls.
--scott

In case anyone missed the reference :-), in Italy Andrea is a male name.

Simon.

[Bill Gunshannon]

Post by Scott Dorsey

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

On the internet, we are all of us beautiful 18-year-old girls.

I thought in the Internet we were all kittens dancing on keyboards.

bill

[Dennis Boone]

Post by Bill Gunshannon
I thought in the Internet we were all kittens dancing on keyboards.

Dogs. We're all dogs, but no one knows.

De

[Paul Sture]

Post by Scott Dorsey

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

On the internet, we are all of us beautiful 18-year-old girls.

Brilliant!

[Scott Dorsey]

Post by Paul Sture

Post by Scott Dorsey

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.

On the internet, we are all of us beautiful 18-year-old girls.

Brilliant!

I cannot take credit. I think Gene Spafford said it in net.singles back
in the eighties.
--scott

[David Turner]

Clair = Male
Claire = Female

If you studied French you would know that right?!?!

Post by Simon Clubley

Post by David Turner
Clair debacle???
What happened?

It was an example of the same mindset that makes some people think
Andrea is always a woman's name.
Simon.

[Camiel Vanderhoeven]

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Same with Camiel / Camille :-)

[Arne Vajhøj]

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Somehow I have a feeling that Richard is not fluent
in french ...

:-)

Arne

[Richard Maher]

Post by Arne Vajhøj

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Somehow I have a feeling that Richard is not fluent
in french ...
:-)
Arne

Here starts to bigoted pseudo intellectual Dutchman who's feeling left
out :-)

I did 3 years Italian (which helped when I had to make a police report
in Italian when someone tried to steal our car) French/German at night
school and lived in Munich for 15 months and developed amazing
restaurant-Deutsch.

Having gone through Catholic school in a immigrant country my Italian is
still being worked on by my high-school mates and the singular o's and
a's and plural e's an i's I'm familiar with.

When your parents named you Arnold on the other hand their aspirational
image of the future was always going to lead to disappointment :-)

War baby? :-)

[Richard Maher]

Post by Richard Maher

Post by Arne Vajhøj

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Somehow I have a feeling that Richard is not fluent
in french ...
:-)
Arne

Here starts to bigoted pseudo intellectual Dutchman who's feeling left
out :-)
I did 3 years Italian (which helped when I had to make a police report
in Italian when someone tried to steal our car) French/German at night
school and lived in Munich for 15 months and developed amazing
restaurant-Deutsch.
Having gone through Catholic school in a immigrant country my Italian is
still being worked on by my high-school mates and the singular o's and
a's and plural e's an i's I'm familiar with.
When your parents named you Arnold on the other hand their aspirational
image of the future was always going to lead to disappointment :-)
War baby? :-)

In fact, if you go to
https://drive.google.com/open?id=0B7Rmd3Rn8_hDMmFqWjlHUG5OQzQ

and look at my meme attempt in nacron.png you'll see that I have a
smattering of French.

Surely, a nation that decided their word for vagina should be
*masculine* is hardly not the best choice for avoiding confusion?

Anyway, back to your narrative of my being an ill-educated beer-swilling
bogan. . .

[a***@yahoo.com]

Post by Richard Maher

Post by Arne Vajhøj

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Somehow I have a feeling that Richard is not fluent
in french ...
:-)
Arne

Here starts to bigoted pseudo intellectual Dutchman who's feeling left
out :-)

I am pretty sure that you don't realize which word in above statement is the most insulting

Post by Richard Maher
I did 3 years Italian (which helped when I had to make a police report
in Italian when someone tried to steal our car) French/German at night
school and lived in Munich for 15 months and developed amazing
restaurant-Deutsch.
Having gone through Catholic school in a immigrant country my Italian is
still being worked on by my high-school mates and the singular o's and
a's and plural e's an i's I'm familiar with.
When your parents named you Arnold on the other hand their aspirational
image of the future was always going to lead to disappointment :-)
War baby? :-)

[Hans Vlems]

Dutchman?

[a***@yahoo.com]

Post by Hans Vlems
Dutchman?

I was hoping that after a hint Richard will figure it out by itself

[Hans Vlems]

Well, I did hope that it was obviously the most unlikely answer....

[a***@yahoo.com]

Post by Hans Vlems
Well, I did hope that it was obviously the most unlikely answer....

Being a proud Dutchman, I assume.

But, of course, I did not mean that Dutchman is insulting world in the absolute sense. The insult is in not caring about fellow poster.

[Richard Maher]

Post by a***@yahoo.com

Post by Hans Vlems
Well, I did hope that it was obviously the most unlikely answer....

Being a proud Dutchman, I assume.
But, of course, I did not mean that Dutchman is insulting world in the absolute sense. The insult is in not caring about fellow poster.

Mate the guy implied I was an uncouth, uncultured, buffoon. Now I have
guilt because I didn't look him up to see if Arne Arnesson was
Icelandic, or Dutch or Danish or whether he used to run the burger
joint on Happy Days.

Look, I don't expect people to be too interested in me and I usually
have to drink to make them interesting. (Only 9 weeks left to City to
Surf which will mark 6 consecutive months on the wagon! Septembers gonna
be ugly :-)

[Dennis Boone]

Post by Arne Vajhøj
Somehow I have a feeling that Richard is not fluent
in french ...

Sacré bleu!

De

[David Froble]

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Richard doesn't even do English well, unless he can use "wanker" every forth or
fifth word ...

[Richard Maher]

Post by David Froble

Post by David Turner
Clair = Male
Claire = Female
If you studied French you would know that right?!?!

Richard doesn't even do English well, unless he can use "wanker" every
forth or fifth word ...

Tu se un branleur mon amie. Un grand branleur!

[Paul Sture]

Post by David Turner

Post by Bob Gezelter

Post by Richard Maher

SWIS Stuff

Thanks for the update!
Has everyone else been able to just proceed in the confidence that you
would succeed and deliver a hardware abstraction compatible with IA64?
Not that it's important but after the Clair debacle I curious about your
name; you're a chick right? I know an middle-eastern Kamiel with a "K".
Also a big "Well done!" and "Keep Going!" to all the engineers who must
get discouraged and ask themselves a few difficult questions from time
to time about the merit of what they're doing. You WILL deliver, and it
WILL pay off!

Richard,
Camiel is not a "chick". (although I will admit not having checked
his passport). His wife and children can confirm.

Clair debacle???
What happened?

From the context, I assume that was when someone mistakenly assumed
that Clair was female.

[David Froble]

Post by David Turner
Clair debacle???
What happened?

Well, for those who pay attention to c.o.v, some months ago Richard considered
"Clair" a female name. Then just recently he considered "Camiel" a female name.

Got to wonder about those Aussies, how they ever manage to reproduce ...

:-)

I could have some more fun with this, but, I better let it go ...

[Dirk Munk]

Post by David Froble

Post by David Turner
Clair debacle???
What happened?

Well, for those who pay attention to c.o.v, some months ago Richard
considered "Clair" a female name.

Actually Clair is an English female name derived from the French female
name Claire, meaning bright.

Post by David Froble
Then just recently he considered "Camiel" a female name.
Got to wonder about those Aussies, how they ever manage to reproduce ...
:-)
I could have some more fun with this, but, I better let it go ...

[Stephen Hoffman]

Post by Dirk Munk

Post by David Froble

Post by David Turner
Clair debacle???
What happened?

Well, for those who pay attention to c.o.v, some months ago Richard
considered "Clair" a female name.

Actually Clair is an English female name derived from the French
female name Claire, meaning bright.

https://medium.com/@malpinder/falsehoods-programmers-believe-about-gender-cf1a55085ab2


Here's one list specific to names, as that's a much bigger mess than
developers might initially realize:

https://www.kalzumeus.com/2010/06/17/falsehoods-programmers-believe-about-names/


There are writing guides and technical writing guides available to
assist folks with gender neutral writing, too.

It'd be interesting to see the OpenVMS technical writing guidelines
posted, but that's entirely up to HPE and VSI.

Some people prefer to refer to this approach as "being politically
correct", while others choose to refer to this writing style as "being
respectful to others".

Here's a handy and curated master list of other common falsehoods:

https://github.com/kdeldycke/awesome-falsehood

[Richard Maher]

https://en.wikipedia.org/wiki/Newspeak#Blackwhite

Post by Stephen Hoffman
Here's one list specific to names, as that's a much bigger mess than
https://www.kalzumeus.com/2010/06/17/falsehoods-programmers-believe-about-names/

https://en.wikipedia.org/wiki/List_of_Newspeak_words

[Richard Maher]

Post by David Turner
Clair debacle???
What happened?

Just that no blokes here are called Clair and I got it wrong but that's
the gender-blind kinda guy I am.

Actually I now work with an English Robin who prefers Rob to avoid
confusion here.

I know a few Dutch people and Dutch TV but never heard of a Camiel.
"Dirk"s yes, Camiels no.

It's like Scandinavians - here's "Eric, "Ivan", and Big Bad "Patsy".

[Dirk Munk]

Post by Richard Maher

Post by David Turner
Clair debacle???
What happened?

Just that no blokes here are called Clair and I got it wrong but
that's the gender-blind kinda guy I am.
Actually I now work with an English Robin who prefers Rob to avoid
confusion here.
I know a few Dutch people and Dutch TV but never heard of a Camiel.
"Dirk"s yes, Camiels no.
It's like Scandinavians - here's "Eric, "Ivan", and Big Bad "Patsy".

Camiel is a Flemish name, so you may find more Camiels in Belgium.
Vanderhoeven could also be Flemish, so he may have Flemish ancestors.
Dutch and Flemish are for 95% identical.

[Richard Maher]

Post by Bob Gezelter
Richard,
Camiel is not a "chick". (although I will admit not having checked his passport). His wife and children can confirm.
- Bob Gezelter, http://www.rlgsc.com

Chicks can have Wives and Children you blithering homophobe - Martina
Navratilova (who wants to rename Margaret Court Arena to Xena Arena :-)

[Milton Baar]

On Monday, June 19, 2017 at 1:53:01 AM UTC+10, Camiel Vanderhoeven wrote:
BIG SNIP
(The X86 hardware provides us only with two useable rings).
Firstly, thanks for the update, extremely informative. Secondly, as an Australian, I understood the non-pejorative use of "chicks"...but the use and responses provided me with some good-natured entertainment, but then I am not Camiel nor Kerry nor Clair so my name has no problematic identifiers...even though they are irrelevant in the usual course of activity.

So to the main question...and I apologise for not being as well informed as others...I thought that X86 did have four hardware states (P0 through P3) but they were unused by most operating systems. Is it that there are only two hardware states and the KESU must be emulated? What CPUs *still* have four hardware states?

[Camiel Vanderhoeven]

Post by Milton Baar
BIG SNIP
(The X86 hardware provides us only with two useable rings).
Firstly, thanks for the update, extremely informative. Secondly, as an Australian, I understood the non-pejorative use of "chicks"...but the use and responses provided me with some good-natured entertainment, but then I am not Camiel nor Kerry nor Clair so my name has no problematic identifiers...even though they are irrelevant in the usual course of activity.
So to the main question...and I apologise for not being as well informed as others...I thought that X86 did have four hardware states (P0 through P3) but they were unused by most operating systems. Is it that there are only two hardware states and the KESU must be emulated? What CPUs *still* have four hardware states?

Well, yes, and no... There are 4 hardware rings on the x86 processor, but not where it counts :-)
The x86 architecture has two memory protection mechanisms: paging, and segmentation. In the 64-bit world, segmentation is almost completely meaningless, as each segment - with a few minor exceptions - covers the entire virtual address space. Now, on the segmentation level, the x86 does indeed have 4 rings, but on the paging level, three of those rings - 1, 2, and 3 - are treated as equal. For VMS, the one thing that distinguishes user, supervisor, and executive mode from each other is the page protection bits, so that's why I wrote that there are only two useable rings on x86.

Camiel

[IanD]

For those wanting to get even a tiny glimpse of Camiel's abilities, watch this youtube and others he put out (1 other for VMS I believe)

Camiel, if you could some more like the one above I would be incredibly happy

BTW

Thanks so much for giving your time to chime in here too

[Camiel Vanderhoeven]

Post by IanD
For those wanting to get even a tiny glimpse of Camiel's abilities, watch this youtube and others he put out (1 other for VMS I believe)
http://youtu.be/6M-7FKhQq8k
Camiel, if you could some more like the one above I would be incredibly happy
BTW
Thanks so much for giving your time to chime in here too

Thanks for the kind words, Ian. I put all three sessions I did at last year's bootcamp up on Youtube:

(please excuse the poor audio quality). I may do this for this year's bootcamp as well.