74LVT transition times: How low can you go?

[Joerg]

Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.

In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

[John Larkin]

On Thu, 01 Mar 2007 00:45:53 GMT, Joerg

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

Sounds reasonable to me. Not a lot can go wrong here.

John

[CBFalconer]

Post by John Larkin

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually
top notch but the family guide for their LVT series is, gasp,
three pages short. Information about maximum transition times on
inputs: Zilch.
In an embedded application I need to slow down the /OE of a
74LVT244 so it turns tri-state fast but goes onto the bus slower,
to avoid a brief contention when addresses change. Is it ok for
that family to slow /OE by 200nsec or so via RC? It'll be the
usual two resistor, one diode and one cap deal. Want to avoid
adding another Schmitt here.

Sounds reasonable to me. Not a lot can go wrong here.

Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.

[Jim Granville]

Post by CBFalconer
Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.

'Destroy the chip' sounds unlikely ?.
Yes, there is a dIcc/dVin peak, but the worst devices I've seen
have this at a few mA - so that's a few milliwatts.

More common is sub mA peaks, and the better devices have this peak
in the uA - like the CPLD we are using here, which has a peak
value of 80uA.
A schmitt Ip gives two peaks,in the Icc/Vin curve, and avoids
transistion oscillation.
-jg

[John Larkin]

Post by CBFalconer

Post by John Larkin

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually
top notch but the family guide for their LVT series is, gasp,
three pages short. Information about maximum transition times on
inputs: Zilch.
In an embedded application I need to slow down the /OE of a
74LVT244 so it turns tri-state fast but goes onto the bus slower,
to avoid a brief contention when addresses change. Is it ok for
that family to slow /OE by 200nsec or so via RC? It'll be the
usual two resistor, one diode and one cap deal. Want to avoid
adding another Schmitt here.

Sounds reasonable to me. Not a lot can go wrong here.

Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.

I think he's talking low duty cycles and fairly rapid slew through the
transition. I doubt the chip temperature would increase measurably.

I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.

Never damaged one, though.

John

[Vladimir Vassilevsky]

Post by John Larkin
I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.
Never damaged one, though.

I did the same experiment with HCT04 gate powered from +5V. At 3.3V
input, it was draining 0.5mA. At 2V at the input, the current was 1mA.
The worst case consumption happened around 0.9V at the input, where it
was about 4mA.

I don't see any problems here.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

[Jim Granville]

Post by Vladimir Vassilevsky

Post by John Larkin
I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.
Never damaged one, though.

I did the same experiment with HCT04 gate powered from +5V. At 3.3V
input, it was draining 0.5mA. At 2V at the input, the current was 1mA.
The worst case consumption happened around 0.9V at the input, where it
was about 4mA.
I don't see any problems here.

From a power aspect, with HCT, you are correct.
With newer devices, that 4mA will go higher, but you'd still
struggle to kill a device.

The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean.
That can cause real problems with downstream devices - I've seen
even unrelated pin drive have edge-oscillation effects that needed
external remedies.

-jg

[CBFalconer]

Jim Granville wrote:
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will be
the time needed for the input to rise (or fall) the hysteresis
voltage.

[Jim Granville]

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will be
the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here.
I'm talking about unwanted transistion oscillation, which can
be in the 100's of MHz region in modern devices.
There is no feedback resistor, and a Schmitt IP does not make
transistion oscillation worse, it removes it.

I think you are thinking of RC oscillators, or even Crystal oscillators
( using unbuffered gates, HCU04 type) which are about the only place
you'd try and do linear feedback, without real care.

-jg

[CBFalconer]

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

[Jim Granville]

Post by CBFalconer

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

You've moved even further from my transistion oscillation instance,
but I'm lost as to what "both transistors are entirely off" can
mean.
I think you mean ONE transistor is entirely off (so no conduction?)
- in a CMOS gate input structure, the only way to have BOTH off, is to
remove the power!

Yes, modern devices can have lower thresholds, but it's not as
bad as you might think, on most logic devices.

I've done a plot of an Atmel ATF1502BE CPLD, ( not your 45nm CPU, but
in a quite modern Logic process )

With the Schmitt enabled, there are two peak currents.

Vin AdderIcc
-----+-------------------------
<0.615 <+1uA ~Off
0.72 +6uA Conduction Tail
0.77 80uA Peak [Falling]
1.000 65uA Peak [Rising]
1.112 +6uA Conduction Tail

Post by CBFalconer
1.23 +1uA ~Off

On this device, below 615mV, or above 1.23V, and there
is effectively no CMOS P-N current path.
Even the peaks are quite low, at 80uA and 65uA, and these are
MUCH lower than a non Schmitt transfer ( IIRC ~45mA narrow Icc Peak )

Drive this from a 1.8V p-p sine-wave, and that averages +8uA of Icc adder.

-jg

[CBFalconer]

Post by Jim Granville

Post by CBFalconer

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

You've moved even further from my transistion oscillation instance,
but I'm lost as to what "both transistors are entirely off" can
mean.

I've been delaying a response, because I beieve somebody has their
head up, and I have come to the conclusion that it is me. I was
thinking of old fashioned 4000 series CMOS, where the transistors
are enhancement mode, with thresholds of something like 8V. At a
Vcc of 12 V no input voltage can turn both units on, but as you
reduce Vcc you come to the condition where both are on at some
input level. I really am not familiar with the characteristics of
the devices forming modern chips, so my opinion becomes relatively
worthless.

[Joerg]

Post by CBFalconer

Post by Jim Granville

Post by CBFalconer

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

You've moved even further from my transistion oscillation instance,
but I'm lost as to what "both transistors are entirely off" can
mean.

I've been delaying a response, because I beieve somebody has their
head up, and I have come to the conclusion that it is me. I was
thinking of old fashioned 4000 series CMOS, where the transistors
are enhancement mode, with thresholds of something like 8V. At a
Vcc of 12 V no input voltage can turn both units on, but as you
reduce Vcc you come to the condition where both are on at some
input level. I really am not familiar with the characteristics of
the devices forming modern chips, so my opinion becomes relatively
worthless.

Threshold is much lower on CD4000 since you can operate them down to 5V
VCC, some of them even at 3V although they become like molasses down there.

The problem is the opposite. Many people including me use them for
analog purposes on occasion. If you bias an inverter that isn't a
Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V
VCC you will get an incredible cross current, to the point where the
chip gets way too hot. Down at 3-5V things are more manageable but you
still have both devices partially on. Just try it out. You can make
quite good amplifiers for next to nothing in cost.

[Jim Granville]

Post by Joerg
Threshold is much lower on CD4000 since you can operate them down to 5V
VCC, some of them even at 3V although they become like molasses down there.
The problem is the opposite. Many people including me use them for
analog purposes on occasion. If you bias an inverter that isn't a
Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V
VCC you will get an incredible cross current, to the point where the
chip gets way too hot. Down at 3-5V things are more manageable but you
still have both devices partially on. Just try it out. You can make
quite good amplifiers for next to nothing in cost.

yup .. and if you current feed them (supply thru a largish resistor) you
can make nice low power (single digit uA region) 32KHz oscillators,
from HEF4069UB.
-jg

[Vladimir Vassilevsky]

Post by Joerg
Threshold is much lower on CD4000 since you can operate them down to 5V
VCC, some of them even at 3V although they become like molasses down there.
The problem is the opposite. Many people including me use them for
analog purposes on occasion. If you bias an inverter that isn't a
Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V
VCC you will get an incredible cross current, to the point where the
chip gets way too hot. Down at 3-5V things are more manageable but you
still have both devices partially on. Just try it out. You can make
quite good amplifiers for next to nothing in cost.

The schematic solutions using 40xx and 74xx as the analog parts were
quite popular and even published in the textbooks about 30 years ago. It
kind of worked, but it never worked for very good. The linearity and the
gain is quite poor. Changing to different logic series required
components change if it worked at all. The CMOS devices operating in the
linear mode were quite easy to fall into the thyristor latchup. So I
would not recommend using the tricks like that for production.


Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

[Joerg]

Post by Vladimir Vassilevsky

Post by Joerg
Threshold is much lower on CD4000 since you can operate them down to
5V VCC, some of them even at 3V although they become like molasses
down there.
The problem is the opposite. Many people including me use them for
analog purposes on occasion. If you bias an inverter that isn't a
Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V
VCC you will get an incredible cross current, to the point where the
chip gets way too hot. Down at 3-5V things are more manageable but you
still have both devices partially on. Just try it out. You can make
quite good amplifiers for next to nothing in cost.

The schematic solutions using 40xx and 74xx as the analog parts were
quite popular and even published in the textbooks about 30 years ago. It
kind of worked, but it never worked for very good. The linearity and the
gain is quite poor. Changing to different logic series required
components change if it worked at all. The CMOS devices operating in the
linear mode were quite easy to fall into the thyristor latchup. So I
would not recommend using the tricks like that for production.

What many of those publications failed to mention is to take a very
close look at the cross current specs (not all parts are spec'd for
that) and set VCC accordingly. Or current limit/source the supply. Else,
yes, it could go kablouie on you.

There are several popular products that use this trick and were in
production for many years, if not decades. One example is the Datong RF
clipper. It's the blue box in the first picture:

http://www.qsl.net/m0ezp/radio-datong.html

I've got one. Stunning performance.

[Jim Granville]

Post by CBFalconer
I've been delaying a response, because I beieve somebody has their
head up, and I have come to the conclusion that it is me. I was
thinking of old fashioned 4000 series CMOS, where the transistors
are enhancement mode, with thresholds of something like 8V. At a
Vcc of 12 V no input voltage can turn both units on, but as you
reduce Vcc you come to the condition where both are on at some
input level. I really am not familiar with the characteristics of
the devices forming modern chips, so my opinion becomes relatively
worthless.

8V thresholds would have to be before my time ? ;)

For the 4000 series devices we use today, have a look at
http://www.standardics.nxp.com/products/hef/pdf/hef4069ub.pdf


In Fig 4., you'll see thresholds in the 1.5-1.75V region.
HCMOS drops that to around 1V, and LVC drops that to
around 0.6V

On the CPLD (ATF1502BE) we measured, the thesholds were
0.63V for NFET ~1uA, and -0.57V for the PFET ~1uA

-jg

[Joerg]

Post by Jim Granville

Post by CBFalconer
I've been delaying a response, because I beieve somebody has their
head up, and I have come to the conclusion that it is me. I was
thinking of old fashioned 4000 series CMOS, where the transistors
are enhancement mode, with thresholds of something like 8V. At a
Vcc of 12 V no input voltage can turn both units on, but as you
reduce Vcc you come to the condition where both are on at some
input level. I really am not familiar with the characteristics of
the devices forming modern chips, so my opinion becomes relatively
worthless.

8V thresholds would have to be before my time ? ;)

Them's were the tube days. Of course, most of those are depletion mode
devices. SCNR.

Post by Jim Granville
For the 4000 series devices we use today, have a look at
http://www.standardics.nxp.com/products/hef/pdf/hef4069ub.pdf
In Fig 4., you'll see thresholds in the 1.5-1.75V region.
HCMOS drops that to around 1V, and LVC drops that to
around 0.6V
On the CPLD (ATF1502BE) we measured, the thesholds were
0.63V for NFET ~1uA, and -0.57V for the PFET ~1uA

And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my hair
is already gone :-(

[Michael A. Terrell]

Post by Joerg
And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my hair
is already gone :-(

Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

[Jim Thompson]

On Wed, 07 Mar 2007 03:41:16 GMT, "Michael A. Terrell"

Post by Michael A. Terrell

Post by Joerg
And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my hair
is already gone :-(

Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

I have the same amount of hair now as I did as a teenager.

It's just that it's moved down to my nose, ears and eyebrows ;-)

...Jim Thompson

[Michael A. Terrell]

Post by Jim Thompson
On Wed, 07 Mar 2007 03:41:16 GMT, "Michael A. Terrell"

Post by Michael A. Terrell
Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

I have the same amount of hair now as I did as a teenager.
It's just that it's moved down to my nose, ears and eyebrows ;-)

When I stop coughing up chunks of phlegm and shaking, (over 10 days
now) I'm going to try to get a decent picture of myself. A new Fuji
Finepix S5200 digital camera was donated to my Veteran's website
project, in trade for help launching a small business website. The
woman wanted some pictures of her shop for her site. I told her that my
camera wasn't very good. She asked what camera I wanted to use, then
she bought the camera so I could take her photos. Then told me to use it
for the Veterans project. :-)

[joseph2k]

Post by Michael A. Terrell

Post by Joerg
And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my hair
is already gone :-(

Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

My first white hairs were noticed at age 14, i was thouroghly salt and
pepper by 17. I have thinned on top but it is still somewhat salt and
pepper decades later. (way heavy on the salt though)

[Michael A. Terrell]

Post by joseph2k

Post by Michael A. Terrell

Post by Joerg
And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my hair
is already gone :-(

Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

My first white hairs were noticed at age 14, i was thouroghly salt and
pepper by 17. I have thinned on top but it is still somewhat salt and
pepper decades later. (way heavy on the salt though)

I was on antibiotics for abscessed teeth for over a month, a couple
years ago. Towards the end of the treatment, some color returned. It
lasted only till it grew out and was replaced with more gray hair. It
was weird having gray hair with brown roots, followed by brown hair with
gray roots. Some research I did years ago suggested bone disease as a
cause for premature gray hair, but I couldn't access the referred
medical journals to do more study.

[joseph2k]

Post by Michael A. Terrell

Post by joseph2k

Post by Michael A. Terrell

Post by Joerg
And the lower it goes the more leakage has to be dealt with. Probably
Jim has pulled his hair at times about that. I couldn't because my
hair is already gone :-(

Damn deserters! ;-) OTOH, I was completely gray by my 22nd birthday.
A jerk that I used to work with loved to tease about it, but I kindly
pointed out that he would never have to worry, because he was already
half bald, and my age. His favorite line was, "Your hair dye can't
handle the job", so I bought one of those temporary kits and used it. It
was an almost perfect match for my hair when I was in high school. The
shocked looks when i walked into work? ;-) Three days later it had
washed out, without a comment. I caught them all together and told them
I know i am 100% gray, but I don't care. You've seen how I used to
look, but you'll never see it again. I'm on the inside, can't see my
hair without looking into a mirror, and really don't care what color it
is so laugh all you want.

My first white hairs were noticed at age 14, i was thouroghly salt and
pepper by 17. I have thinned on top but it is still somewhat salt and
pepper decades later. (way heavy on the salt though)

I was on antibiotics for abscessed teeth for over a month, a couple
years ago. Towards the end of the treatment, some color returned. It
lasted only till it grew out and was replaced with more gray hair. It
was weird having gray hair with brown roots, followed by brown hair with
gray roots. Some research I did years ago suggested bone disease as a
cause for premature gray hair, but I couldn't access the referred
medical journals to do more study.

My grey hair is a known genetic attribute, my mum's hair was nearly white by
age 18, and her mum's hair was white by 14 but thick and wavy into her
90's.

[Paul Keinanen]

Post by CBFalconer

Post by Jim Granville

Post by CBFalconer

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

You've moved even further from my transistion oscillation instance,
but I'm lost as to what "both transistors are entirely off" can
mean.

I've been delaying a response, because I beieve somebody has their
head up, and I have come to the conclusion that it is me. I was
thinking of old fashioned 4000 series CMOS, where the transistors
are enhancement mode, with thresholds of something like 8V. At a
Vcc of 12 V no input voltage can turn both units on, but as you
reduce Vcc you come to the condition where both are on at some
input level. I really am not familiar with the characteristics of
the devices forming modern chips, so my opinion becomes relatively
worthless.

I am not sure what you mean by old fashioned 4000 series CMOS, but at
least the "McMos Handbook" second edition (1974) from Motorola at page
3-15 display the Idd for MC14011AL NAND gate for Vdd 10 and 15 volts.

At Vdd = 10 V, the drain current starts to rise at 1.5 V input voltage
reaching a peak of about 2 mA at 4,5 V and falling back to zero at 8
V.

At Vdd=15 V, the drain current starts to rise at 2 V reaching a peak
of 5-6.5 mA at 6,5 V and falling back to zero at 13 V.

Clearly both transistors are on even with Vdd=10 V for a long period
of time.

About the question could the device self destruct due to too much
heat, taking the peak current of 6.5 mA and the 15 V supply voltage,
this is only 100 mW and with 4-6 elements in a package, we are talking
about 400-600 mW, which is quite a lot for a 14-16 pin DIP package,
but at least not destroy the package immediately.

Paul

[Joerg]

Post by CBFalconer

Post by CBFalconer
... snip ...

Post by Jim Granville
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will
be the time needed for the input to rise (or fall) the hysteresis
voltage.

You've lost me here. I'm talking about unwanted transistion
oscillation, which can be in the 100's of MHz region in modern
devices. There is no feedback resistor, and a Schmitt IP does not
make transistion oscillation worse, it removes it.
I think you are thinking of RC oscillators, or even Crystal
oscillators ( using unbuffered gates, HCU04 type) which are about
oscillators you'd try and do linear feedback, without real care.

There is always feedback, possibly only via the capacitance between
input and output. It is possible that the leakage current into the
input pin is so small that the system becomes quiescent, but not
too likely. That is why one normally ties unused inputs to ground
(or Vcc). With, say 12V CMOS it is possible to bias the input pin
so that both transistors are entirely off, and the system is
stable. This is one of the curses of low Vcc CMOS logic - there is
no real stable point where both input transistors are firmly off.

That can also be a blessing when you want to make a really cheap amp.

[Jim Granville]

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

Hi Joerg,

Philips used to claim Schmitt Ips on these ? (well, the LVC series )
(but not everyone does..)

Their LVC244 data says this:
(as does the LVC2244A, which we have just used )

" Schmitt-trigger action at all inputs makes the circuit highly tolerant
for slower input rise and fall times." -


-jg

[Joerg]

Post by Jim Granville

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

Hi Joerg,
Philips used to claim Schmitt Ips on these ? (well, the LVC series )
(but not everyone does..)
(as does the LVC2244A, which we have just used )
" Schmitt-trigger action at all inputs makes the circuit highly tolerant
for slower input rise and fall times." -

Hmm, interesting, where did you find that?

[John F]

Post by Joerg

Post by Jim Granville
" Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times." -

Hmm, interesting, where did you find that?

Attention: He is talking about lvC and you about lvT!

[Jim Granville]

Post by Joerg

Post by Jim Granville

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor,
one diode and one cap deal. Want to avoid adding another Schmitt here.

Hi Joerg,
Philips used to claim Schmitt Ips on these ? (well, the LVC series )
(but not everyone does..)
(as does the LVC2244A, which we have just used )
" Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times." -

Hmm, interesting, where did you find that?

Try page 2 of this
http://www.standardics.nxp.com/products/lvc/pdf/74lvc2244a.pdf

I think the LVC is the more modern family, with the LVT being phased
out ?

-jg

[Joerg]

Post by Jim Granville

Post by Joerg

Post by Jim Granville

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three
Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor,
one diode and one cap deal. Want to avoid adding another Schmitt here.

Hi Joerg,
Philips used to claim Schmitt Ips on these ? (well, the LVC series )
(but not everyone does..)
(as does the LVC2244A, which we have just used )
" Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times." -

Hmm, interesting, where did you find that?

Try page 2 of this
http://www.standardics.nxp.com/products/lvc/pdf/74lvc2244a.pdf
I think the LVC is the more modern family, with the LVT being phased
out ?

Are your sure the LVT is going? I am not too familiar with modern logic,
as an analog guy I usually get away with 74HC and CD4000.

Anyhow, this LVC driver doesn't look like Schmitt, it says 10nsec max
transisitions on the inputs when using it at 3.3V. Our bus will not even
be that fast. On purpose, for EMI reasons.

[Jim Granville]

Post by Joerg

Post by Jim Granville

Post by Joerg

Post by Jim Granville
" Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times." -

Hmm, interesting, where did you find that?

Try page 2 of this
http://www.standardics.nxp.com/products/lvc/pdf/74lvc2244a.pdf
I think the LVC is the more modern family, with the LVT being phased
out ?

Are your sure the LVT is going? I am not too familiar with modern logic,
as an analog guy I usually get away with 74HC and CD4000.

Look at the dates on the data sheets, and the lack of a 'new' category
on their web site.

There were too many low voltage logics, and they seem to be slowly
rationalising to two wide voltage familes, the LVC and the AUP

Post by Joerg
Anyhow, this LVC driver doesn't look like Schmitt, it says 10nsec max
transisitions on the inputs when using it at 3.3V. Our bus will not even
be that fast. On purpose, for EMI reasons.

It explicitly says so in the data (above) - so where you have a conflict
like this, grab a device and try it :)

Often they still spec a Tr/Tf, in order for all the timing to be valid.
eg if they allowed a slow data rise, and a slow clock rise, then the
threshold match comes into play - so they give a test tr/tf, which
mitigates threshold effects, and makes all the ns specs valid.

Just try one: Ramp the inputs, and measure the Icc and output - there
will be a Icc/Vin relationship, that is not always given, and on
some devices that can be what I'd call poor. Probably does not matter
in your design.

-jg

[Joerg]

Post by Jim Granville

Post by Joerg

Post by Jim Granville

Post by Joerg

Post by Jim Granville
" Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times." -

Hmm, interesting, where did you find that?

Try page 2 of this
http://www.standardics.nxp.com/products/lvc/pdf/74lvc2244a.pdf
I think the LVC is the more modern family, with the LVT being phased
out ?

Are your sure the LVT is going? I am not too familiar with modern
logic, as an analog guy I usually get away with 74HC and CD4000.

Look at the dates on the data sheets, and the lack of a 'new' category
on their web site.
There were too many low voltage logics, and they seem to be slowly
rationalising to two wide voltage familes, the LVC and the AUP

Thanks for the info, always good to know what's on the way to becoming
unobtanium.

Post by Jim Granville

Post by Joerg
Anyhow, this LVC driver doesn't look like Schmitt, it says 10nsec max
transisitions on the inputs when using it at 3.3V. Our bus will not
even be that fast. On purpose, for EMI reasons.

It explicitly says so in the data (above) - so where you have a conflict
like this, grab a device and try it :)
Often they still spec a Tr/Tf, in order for all the timing to be valid.
eg if they allowed a slow data rise, and a slow clock rise, then the
threshold match comes into play - so they give a test tr/tf, which
mitigates threshold effects, and makes all the ns specs valid.
Just try one: Ramp the inputs, and measure the Icc and output - there
will be a Icc/Vin relationship, that is not always given, and on
some devices that can be what I'd call poor. Probably does not matter
in your design.

Or maybe I just place a couple Schmitt inverters to, as Jim put it, "do
it right".

[Jim Granville]

Post by Joerg
Or maybe I just place a couple Schmitt inverters to, as Jim put it, "do
it right".

You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.

To my mind, all logic should have hysteresis by default, but I
do note that the new universal gates 1G57/58/97/98 all have hystersis.
( and the better CPLDs now have it selectable by pin )

If you need to start using 'fixup gates', have a look at those
universal gate series.
With one of those, you should be able to save 2 if your passives.

-jg

[Joerg]

Post by Jim Granville

Post by Joerg
Or maybe I just place a couple Schmitt inverters to, as Jim put it,
"do it right".

You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.

Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can then
happily ignore those. Unfortunately only NXP mentions Schmitts, TI
doesn't unless I overlooked something. And NXP is out of stock :-(

Post by Jim Granville
To my mind, all logic should have hysteresis by default, but I
do note that the new universal gates 1G57/58/97/98 all have hystersis.
( and the better CPLDs now have it selectable by pin )

Agree, it all should. Would make life much easier.

Post by Jim Granville
If you need to start using 'fixup gates', have a look at those
universal gate series.
With one of those, you should be able to save 2 if your passives.

[Jim Granville]

Post by Joerg

Post by Jim Granville
You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.

Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can then
happily ignore those.

See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.

Post by Joerg
Unfortunately only NXP mentions Schmitts, TI
doesn't unless I overlooked something.

I just looked at IDT's offering, they spec :
VH Input Hysteresis VCC = 3.3V 100mV typ

Post by Joerg
And NXP is out of stock :-(

74LVC244A shows at Future and Digikey, in most packages ?

Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.

-jg

[Joerg]

Post by Jim Granville

Post by Joerg

Post by Jim Granville
You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.

Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can
then happily ignore those.

See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.

Post by Joerg
Unfortunately only NXP mentions Schmitts, TI doesn't unless I
overlooked something.

VH Input Hysteresis VCC = 3.3V 100mV typ

Post by Joerg
And NXP is out of stock :-(

74LVC244A shows at Future and Digikey, in most packages ?

Yes, indeed. I was looking at the one you had suggested further above,
the LVC2244 where there is no stock. Still, it's somewhat uncomfortable
to have to release only one manufacturer and ban others for the same
chip. But it sure ain't the first time.

Thanks again for the hint. The LVC244 (from NXP) looks like a good chip.

Post by Jim Granville
Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.

Yes, but I got used to it. Bought 3x glasses for lab work when TSSOP
came out ;-)

Meantime I became a bit careful if a chip is not migrated to TSSOP
because that could be an indicator that it's heading to lalaland.

[John F]

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor,
one diode and one cap deal. Want to avoid adding another Schmitt
here.

100mV/ns and 1/2 µs are specified.

I'd go with that solution.

[Vladimir Vassilevsky]

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.
But the 200ns seems like an awful long time. Why would you need that?

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

[Joerg]

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

Post by Vladimir Vassilevsky
But the 200ns seems like an awful long time. Why would you need that?

I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

[Vladimir Vassilevsky]

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor,
one diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.

VLV

[Joerg]

Post by Vladimir Vassilevsky

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor,
one diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.

There is, however, a cost difference. A BAV70 runs you about a cent or
two. But in this app that wouldn't matter (it usually does in my apps
though).

[rickman]

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

Post by Vladimir Vassilevsky
But the 200ns seems like an awful long time. Why would you need that?

I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

[Vladimir Vassilevsky]

Post by rickman
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly".

Good point. This is shamanism however it has to be done sometimes.
Remember the pull-up resistor on Z80 clock input? The modern CPUs have
the provision for picosecond timing adjustment on the signals.


I'm not

Post by rickman
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to.

Diode in series with the resistor plus the other resistor in parallel.
Cap to the ground. The falling front is delayed, the raising front is
also delayed but for less amount of time.


I think that (in opposition to my training) there are

Post by rickman
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

As usual, it is nothing wrong the tricks like that as long as one
clearly knows what he is doing and what are the other implications.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

[rickman]

Post by Vladimir Vassilevsky
Diode in series with the resistor plus the other resistor in parallel.
Cap to the ground. The falling front is delayed, the raising front is
also delayed but for less amount of time.

This is one of those circuits that may work ok and may not. The diode
drop will cause a noticable voltage drop. So the fast edge will rise/
fall to a point and then trail out to the "proper" voltage level.
Both edges will suffer from increased noise sensitivity due to the
slowed edge rate. This may or may not be an issue with your design
depending on the noise level. A schmitt trigger will deal with the
slowed signal edges much more effectively, but may be overkill for any
given app. I have not seen too many diodes that are significantly
smaller than one of the pico gates, so I don't use them for anything
other than ESD protection.

[CBFalconer]

rickman wrote:
... snip ...

Post by rickman
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

A diode into a RC pullup network can give a fast attack (for
negative transitions) and a controlled rise time (for positive
transitions). This assumes the driver can handle the negative
going current and that the receiver can stand the one diode drop
from ground level. Without the capacitor it can also be a
simple-minded level shifter.

[Joerg]

Post by rickman

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

Post by Vladimir Vassilevsky
But the 200ns seems like an awful long time. Why would you need that?

I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Post by rickman
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.

Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran :-)))

[Jim Granville]

Joerg wrote:
<snip>

Post by Joerg
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables.

Care to elaborate why ?

Post by Joerg
There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

In these situations (hand-over uncertainty), I've also seen simple
series resistors used. They keep the currents to safe levels, and
permit some latency tolerance, and normally the time frames are
short.

-jg

[Joerg]

Post by Jim Granville
<snip>

Post by Joerg
Not really, unless I use a CPLD here which I don't want to. These
board should not contain any programmables.

Care to elaborate why ?

Programming is a hassle, we want to be able to just populate the boards,
test and plug them in.

Post by Jim Granville

Post by Joerg
There are SPI devices and these only have one enable, not /OE plus
/CE. BTW they use various names for that pin. Even within the same
company (Analog Devices) it's called /SYNC on the DACs I am using and
/CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

In these situations (hand-over uncertainty), I've also seen simple
series resistors used. They keep the currents to safe levels, and
permit some latency tolerance, and normally the time frames are
short.

We could do that but there'll be a whole lot of boards in the unit and
thus a pretty large backplane that needs to be driven. Plus the digital
designer for the other stuff really would like Thevenin. But with
Schmitt inputs it'll be ok.

[rickman]

Post by Joerg
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

Now this is beginning to make some sense.

Post by Joerg
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

Post by Joerg
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.

The reason to be careful combining digital and analog in these ways is
because of how the digital thresholds vary over temperature, voltage
and process. You can model, test and analyze, but you still need to
allow plenty of margin for things you don't easily control such as
process variation and noise.

Heck, I saw a circuit that simply used a FET to control the current
through an LED. But the transfer characteristics of the FET are not
well controlled. After two years of use in a design they tweeked
their process and the circuit stopped working due to the rise in
threshold voltage. Not a lot, just enough to make the LEDs too dim to
really see.

[Vladimir Vassilevsky]

Post by rickman
Heck, I saw a circuit that simply used a FET to control the current
through an LED.

Great. I have seen bunch of leds connected in parallel. Another good one
is driving a led by logic '1' directly from a chip. But the best
solution I ever heard of is using comparator as opamp in the measurement
circuit! And after that somebody complains about the software...

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

[Genome]

Post by Vladimir Vassilevsky

Post by rickman
Heck, I saw a circuit that simply used a FET to control the current
through an LED.

Great. I have seen bunch of leds connected in parallel. Another good one
is driving a led by logic '1' directly from a chip. But the best solution
I ever heard of is using comparator as opamp in the measurement circuit!
And after that somebody complains about the software...
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Not wishing to set you off but I'd take a guess that these analog
'solutions' were implemented by 'digital/software' engineers.......

DNA

[Joerg]

Post by Genome

Post by Vladimir Vassilevsky

Post by rickman
Heck, I saw a circuit that simply used a FET to control the current
through an LED.

Great. I have seen bunch of leds connected in parallel. Another good one
is driving a led by logic '1' directly from a chip. But the best solution
I ever heard of is using comparator as opamp in the measurement circuit!
And after that somebody complains about the software...
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Not wishing to set you off but I'd take a guess that these analog
'solutions' were implemented by 'digital/software' engineers.......

Sometimes they are cooked up by very cost-conscious all-round designers.
My "mentor circuit" was a product from your country, the Datong
RF-clipper (it clips audio without intermod). They used CD4000 logic
chips in analog fashion all over the place. And I guess they made tons
of money. In fact, these things were so great that a rock guitarist
absolutely wanted to keep mine after I gave it to him for a week. He was
blown away, said he's never heard the rafters shake and the glass rattle
so good when playing "Stairway to Heaven". After I told him that I
really wanted it back he ordered one the next day.

[Joerg]

Post by rickman

Post by Joerg
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

Now this is beginning to make some sense.

Post by Joerg
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

Well, we opted for a bare bones bus where the adresses do that :-)

Post by rickman

Post by Joerg
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.

The reason to be careful combining digital and analog in these ways is
because of how the digital thresholds vary over temperature, voltage
and process. You can model, test and analyze, but you still need to
allow plenty of margin for things you don't easily control such as
process variation and noise.

That's why I like Schmitts. Unless I want to use an logic inverter as a
linear amp...

Post by rickman
Heck, I saw a circuit that simply used a FET to control the current
through an LED. But the transfer characteristics of the FET are not
well controlled. After two years of use in a design they tweeked
their process and the circuit stopped working due to the rise in
threshold voltage. Not a lot, just enough to make the LEDs too dim to
really see.

Thou shalt not go by the typical Rdson versus Vgs graph but always by
the guaranteed values.

[rickman]

Post by Joerg

Post by rickman
Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

Well, we opted for a bare bones bus where the adresses do that :-)

Maybe I still don't understand what you are doing. Are you saying
that the controller does not generate a timing strobe at all? Even if
there is a single timing strobe combined with the address lines, that
would work fine. The controller just has to deactivate the enable
long enough for the address to change and the decoders to get stable
inputs. If you are not using a timing strobe (enable) then you are
asking for trouble. The decoders can generate glitches that can cause
the receiving circuits to think they saw an enable with no clock
pulses. This can cause all sorts of malfunctions. I don't know about
your specific circuits, but I would not try this with or without the
analog delays in the timing.

Post by Joerg
That's why I like Schmitts. Unless I want to use an logic inverter as a
linear amp...

But you still have to understand the digital circuitry and how to
generate correct timing. Or am I missing something about your
design?

Post by Joerg
Thou shalt not go by the typical Rdson versus Vgs graph but always by
the guaranteed values.

Yes, I am sure the designer learned a bit about that. I am surprised
it took a process change to cause failures actually.

[Robert Adsett]

In article <***@h3g2000cwc.googlegroups.com>,
rickman says...

Post by rickman

Post by Joerg
Thou shalt not go by the typical Rdson versus Vgs graph but always by
the guaranteed values.

Yes, I am sure the designer learned a bit about that. I am surprised
it took a process change to cause failures actually.

I saw a design a few years back where an RC between two Schmidt input
inverters was used as a delay element. Years into production they
started getting failures. It turned out that the timing was ultimately
controlled not by the RC but by the current drive capabilities of the
inverter. They had changed to an equivalent part from another supplier
and it's drive current limit was different.

Robert

[Joerg]

Post by rickman

Post by Joerg

Post by rickman
Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

Well, we opted for a bare bones bus where the adresses do that :-)

Maybe I still don't understand what you are doing. Are you saying
that the controller does not generate a timing strobe at all? Even if
there is a single timing strobe combined with the address lines, that
would work fine. The controller just has to deactivate the enable
long enough for the address to change and the decoders to get stable
inputs. If you are not using a timing strobe (enable) then you are
asking for trouble. The decoders can generate glitches that can cause
the receiving circuits to think they saw an enable with no clock
pulses. This can cause all sorts of malfunctions. I don't know about
your specific circuits, but I would not try this with or without the
analog delays in the timing.

Poor man's strobe, via the enable inputs of several HC688 decoders :-)))

That works, as long as wait times are maintained and no data transfer
happens unless the addresses are held stable.

Post by rickman

Post by Joerg
That's why I like Schmitts. Unless I want to use an logic inverter as a
linear amp...

But you still have to understand the digital circuitry and how to
generate correct timing. Or am I missing something about your
design?

Yes, one has to. That's why I like to run busses with zero contention,
not even for a few nsec. Some may say it's ok for a short time sliver
but my take is that it isn't meant to be and it also generates EMI
headaches. Or at least EMI worries. I don't want the client to come back
from UL with a black eye because this bus caused a few peaks to stick
out beyond class B limits.

Post by rickman

Post by Joerg
Thou shalt not go by the typical Rdson versus Vgs graph but always by
the guaranteed values.

Yes, I am sure the designer learned a bit about that. I am surprised
it took a process change to cause failures actually.

[Hal Murray]

Post by Joerg
Poor man's strobe, via the enable inputs of several HC688 decoders :-)))

Do you have an AND gate anywhere in the path generating those enables?

If so, make the gate 1 term wider and run the signal that makes
the leading edge through a non-inverting buffer and into the
and gate. That will delay the turn-on by a gate delay.

(Stand on your head as required to get the polarities to work
out right.)

You probably can't prove no-contention by just reading the data
sheets because the turn on/off specs cover voltage and temperature.
But you might be able to convince yourself it will work OK after
spending some time in the lab.

[Joerg]

Post by Hal Murray

Post by Joerg
Poor man's strobe, via the enable inputs of several HC688 decoders :-)))

Do you have an AND gate anywhere in the path generating those enables?

Only one AND chip and it's already fully occupied :-(

Post by Hal Murray
If so, make the gate 1 term wider and run the signal that makes
the leading edge through a non-inverting buffer and into the
and gate. That will delay the turn-on by a gate delay.
(Stand on your head as required to get the polarities to work
out right.)
You probably can't prove no-contention by just reading the data
sheets because the turn on/off specs cover voltage and temperature.
But you might be able to convince yourself it will work OK after
spending some time in the lab.

With the RC that has two time constants (and a Schmitt) it'll work fine.

[Jim Thompson]

On Sun, 04 Mar 2007 21:52:33 GMT, Joerg

Post by Joerg

Post by Hal Murray

Post by Joerg
Poor man's strobe, via the enable inputs of several HC688 decoders :-)))

Do you have an AND gate anywhere in the path generating those enables?

Only one AND chip and it's already fully occupied :-(

Post by Hal Murray
If so, make the gate 1 term wider and run the signal that makes
the leading edge through a non-inverting buffer and into the
and gate. That will delay the turn-on by a gate delay.
(Stand on your head as required to get the polarities to work
out right.)
You probably can't prove no-contention by just reading the data
sheets because the turn on/off specs cover voltage and temperature.
But you might be able to convince yourself it will work OK after
spending some time in the lab.

With the RC that has two time constants (and a Schmitt) it'll work fine.

I just remembered this...

http://analog-innovations.com/SED/CrudeDelay.pdf

Lose the XOR for your purposes.

This has delay plus snap action, so the edges don't get perverted like
with typical RC delays.

...Jim Thompson

[Hal Murray]

Post by rickman
Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

I know of several clean solutions.

The simplest is to leave a dead cycle between enables. That has
the obbvious drawback of wasting a lot of time on the bus.

Another approach is to only enable the drivers for the last 1/2 or 3/4
of each cycle. This can be free if you are using something like
a '138 to select which chip drives the bus since it has an enable
pin where you can connect the clock.

Sometimes you can add a gate delay - that is delay the enable
until the previous enable is off in such a way that it takes
one level of logic. This may be easier if you are already using
a PAL.

Another approach is to just ignore the problem. I'm pretty sure
I've seen an app-note someplace that says the turn off is faster
than the turn on just for this reason. That only work if you are
using the same logic family for all your bus drivers, and maybe
you need same voltage/temp too. A test card and some time in
the lab might be worthwhile.

It's probably a lot more reasonable to ignore the contention if
you are using the chips with the built in series damping resistors.
They will limit any current spikes.

[Joerg]

Post by Hal Murray

Post by rickman
Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

I know of several clean solutions.
The simplest is to leave a dead cycle between enables. That has
the obbvious drawback of wasting a lot of time on the bus.
Another approach is to only enable the drivers for the last 1/2 or 3/4
of each cycle. This can be free if you are using something like
a '138 to select which chip drives the bus since it has an enable
pin where you can connect the clock.
Sometimes you can add a gate delay - that is delay the enable
until the previous enable is off in such a way that it takes
one level of logic. This may be easier if you are already using
a PAL.
Another approach is to just ignore the problem. I'm pretty sure
I've seen an app-note someplace that says the turn off is faster
than the turn on just for this reason. That only work if you are
using the same logic family for all your bus drivers, and maybe
you need same voltage/temp too. A test card and some time in
the lab might be worthwhile.
It's probably a lot more reasonable to ignore the contention if
you are using the chips with the built in series damping resistors.
They will limit any current spikes.

Ignoring can come with penalties. I am often called out to clients after
they failed at the EMC lab. Wish they'd call me before but it's like at
the dentist, most of us go there after the pain has become unbearable or
a molar just broke (had that happen last week). Anyhow, I have found
"innocent" bus contentions to be the root cause of such failures more
than once.

[John Larkin]

On Fri, 02 Mar 2007 18:23:20 GMT, Joerg

Post by Joerg

Post by rickman

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

Post by Vladimir Vassilevsky
But the 200ns seems like an awful long time. Why would you need that?

I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Why bother? A little transient bus contention never hurt anybody.

John

[Joerg]

Post by John Larkin
On Fri, 02 Mar 2007 18:23:20 GMT, Joerg

Post by Joerg

Post by rickman

Post by Joerg

Post by Vladimir Vassilevsky

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

You can make a delay using something like 1G97.

I could also do it with a 74HC14 but I wanted to avoid more chips.

Post by Vladimir Vassilevsky
But the 200ns seems like an awful long time. Why would you need that?

I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Why bother? A little transient bus contention never hurt anybody.

But when that lets off a wee EMI birdie the Federales might be swooping
down on ya some day ;-)

Seriously, this gear is used in medical settings and there everything
needs to be nice, quiet and class B or better.

[Vladimir Vassilevsky]

Post by Joerg
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay.
Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran :-)))

I see. You want to be more holy than a Pope, Larkin and Rickman
altogether, that is what this circuit for :)))

VLV

[Joerg]

Post by Vladimir Vassilevsky

Post by Joerg
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay.
Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran :-)))

I see. You want to be more holy than a Pope, Larkin and Rickman
altogether, that is what this circuit for :)))

"Holier than thou" is just what our pastor keeps hammering into us not
to ever think, pretend or live ;-)

[Clifford Heath]

Post by Joerg
"Holier than thou" is just what our pastor keeps hammering into us not
to ever think, pretend or live ;-)

And yet you believe him, thus accepting he's holier than you.

"Sans dieu, sans maitre". Be your own arbiter, think your own thoughts.

[Joerg]

Post by Clifford Heath

Post by Joerg
"Holier than thou" is just what our pastor keeps hammering into us not
to ever think, pretend or live ;-)

And yet you believe him, thus accepting he's holier than you.

No, I believe in God.

Post by Clifford Heath
"Sans dieu, sans maitre". Be your own arbiter, think your own thoughts.

Own thoughts, yes. Own arbiter, that don't work IMHO.

[Clifford Heath]

Post by Joerg

Post by Clifford Heath
And yet you believe him, thus accepting he's holier than you.

No, I believe in God.

I hope you didn't mind my gentle dig. I've been there too, for
a couple of decades, not spanning my childhood. Before you can
believe in God, you believe in your ability to choose what to
believe in. No matter what you tell yourself, it starts and ends
with you. When you repudiate that, you repudiate your essential
humanity. IME most pastors have more opinions than experience
anyway. Why trust someone for advice on life, when they get paid
*not* to live the kind of life *you* live?

[Joerg]

Post by Clifford Heath

Post by Joerg

Post by Clifford Heath
And yet you believe him, thus accepting he's holier than you.

No, I believe in God.

I hope you didn't mind my gentle dig. I've been there too, for
a couple of decades, not spanning my childhood. Before you can
believe in God, you believe in your ability to choose what to
believe in. No matter what you tell yourself, it starts and ends
with you. When you repudiate that, you repudiate your essential
humanity. IME most pastors have more opinions than experience
anyway. Why trust someone for advice on life, when they get paid
*not* to live the kind of life *you* live?

We are lucky to have a pastor who lives his life very well IMHO. In our
church we use the bible as the yardstick as to what is "well".
Unfortunately a lot of other denominations don't.

[Yuriy K.]

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.

http://www.google.com/search?hl=en&q=phillips+lvt&btnG=Google+Search

http://www.standardics.nxp.com/support/documents/logic/pdf/family.lvt.specification.pdf
...
RECOMMENDED OPERATING CONDITIONS
...
Dt/Dv Input transition rise or fall rate; Outputs enabled : <10 ns/V
...

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

Not according to specs.

http://www.standardics.nxp.com/products/lvt/pdf/74lvt2244.pdf
...
9. Recommended operating conditions:
...
Dt/DV input transition rise and fall rate; outputs enabled : <10 ns/V

[Joerg]

Post by Yuriy K.

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.

http://www.google.com/search?hl=en&q=phillips+lvt&btnG=Google+Search
http://www.standardics.nxp.com/support/documents/logic/pdf/family.lvt.specification.pdf
...
RECOMMENDED OPERATING CONDITIONS
...
Dt/Dv Input transition rise or fall rate; Outputs enabled : <10 ns/V
...

Post by Joerg
In an embedded application I need to slow down the /OE of a 74LVT244
so it turns tri-state fast but goes onto the bus slower, to avoid a
brief contention when addresses change. Is it ok for that family to
slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
diode and one cap deal. Want to avoid adding another Schmitt here.

Not according to specs.
http://www.standardics.nxp.com/products/lvt/pdf/74lvt2244.pdf
...
...
Dt/DV input transition rise and fall rate; outputs enabled : <10 ns/V

I had the LVT244 in mind (sans terminator), not the LVT2244. For some
reason the NXP server doesn't find its data sheet anymore this morning.
Arrgh. Well, at least Digikey has a few thousand of them.

[Jim Thompson]

On Thu, 01 Mar 2007 00:45:53 GMT, Joerg

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

Sure is a _crude_ way to get a timing delay. Why not do it right ?:-)

...Jim Thompson

[Joerg]

Post by John Larkin
On Thu, 01 Mar 2007 00:45:53 GMT, Joerg

Post by Joerg
Specsmanship seems to be on the decline. Philips/NXP is usually top
notch but the family guide for their LVT series is, gasp, three pages
short. Information about maximum transition times on inputs: Zilch.
In an embedded application I need to slow down the /OE of a 74LVT244 so
it turns tri-state fast but goes onto the bus slower, to avoid a brief
contention when addresses change. Is it ok for that family to slow /OE
by 200nsec or so via RC? It'll be the usual two resistor, one diode and
one cap deal. Want to avoid adding another Schmitt here.

Sure is a _crude_ way to get a timing delay. Why not do it right ?:-)

Yeah, I know. If it had Schmitts it would be ok. Guess it ain't...

[Genome]

Specsmanship seems to be on the decline. Philips/NXP is usually top notch
but the family guide for their LVT series is, gasp, three pages short.
Information about maximum transition times on inputs: Zilch.
--
Regards, Joerg
http://www.analogconsultants.com

This is standard practice when divisions of companies like Siemens or
Philips get sold off, broken up or reincarnated. Ultimately all the useful
data which you used to able to download as a single big book gets split up
into lots of little pieces that are then smeared about the new abortion of a
website and in the process a lot of it just disappears.

It's either job creation, stupidity or job creation for stupid people. The
final goal is to force you to contact an application stupid person using a
stupid web form that is invariably hidden behind a registration stupid web
form.

If you want the information you might try it but invariably you'll become

Mr Bum Bollocks
Bum Bollocks & Co Ltd
Bum Street
Bollockshampton

Just so you can say something like......

Re your p/n 123XYZ

I have just placed my order for 24,999,678 units with Not Your Company Ltd

Kindest ETC

Mr Bollocks

[Joerg]

Post by Genome

Specsmanship seems to be on the decline. Philips/NXP is usually top notch
but the family guide for their LVT series is, gasp, three pages short.
Information about maximum transition times on inputs: Zilch.
--
Regards, Joerg
http://www.analogconsultants.com

This is standard practice when divisions of companies like Siemens or
Philips get sold off, broken up or reincarnated. Ultimately all the useful
data which you used to able to download as a single big book gets split up
into lots of little pieces that are then smeared about the new abortion of a
website and in the process a lot of it just disappears.
It's either job creation, stupidity or job creation for stupid people. The
final goal is to force you to contact an application stupid person using a
stupid web form that is invariably hidden behind a registration stupid web
form.

Yeah, it's sad. This moring the NXP server has become unable to even
find the LVT244 datasheet. &*#^!!. Link broken. Sometimes it is
unbelievable what people do to a formerly well-oiled machinery. What a
great company this had been in the 80's. Sad.

Post by Genome
If you want the information you might try it but invariably you'll become
Mr Bum Bollocks
Bum Bollocks & Co Ltd
Bum Street
Bollockshampton
Just so you can say something like......
Re your p/n 123XYZ
I have just placed my order for 24,999,678 units with Not Your Company Ltd
Kindest ETC
Mr Bollocks

I stopped writing to top brass about serious issues a company has.
Because they rarely listen. So I just quietly skadaddle over to the
competition.