Alec Roelke
2016-09-14 22:45:02 UTC
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:80e562ddf946
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
a.out 8bc53d5565ba
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:80e562ddf946
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
a.out 8bc53d5565ba
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke