Daniel Carvalho (Gerrit)
2018-02-20 10:33:17 UTC
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/8501
Change subject: mem-cache: Split array indexing and replacement policies.
......................................................................
mem-cache: Split array indexing and replacement policies.
Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:
- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.
For this reason, they were split into different classes. Advantages:
- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes
As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).
Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
---
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
A src/mem/cache/replacement_policies/ReplacementPolicies.py
A src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/base.cc
A src/mem/cache/replacement_policies/base.hh
A src/mem/cache/replacement_policies/lru_rp.cc
A src/mem/cache/replacement_policies/lru_rp.hh
A src/mem/cache/replacement_policies/random_rp.cc
A src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/tags/SConscript
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
D src/mem/cache/tags/lru.cc
D src/mem/cache/tags/lru.hh
D src/mem/cache/tags/random_repl.cc
D src/mem/cache/tags/random_repl.hh
M tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
M
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
M
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
M tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
M tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
M tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
M tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
M tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
M tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
M tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
M
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
M
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
M tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
43 files changed, 880 insertions(+), 444 deletions(-)
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py
b/configs/common/cores/arm/O3_ARM_v7a.py
index fde4d3c..b0ba128 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -201,4 +201,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/configs/common/cores/arm/ex5_LITTLE.py
b/configs/common/cores/arm/ex5_LITTLE.py
index a866b16..1ae0f16 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -145,6 +145,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=1, latency = 1)
- tags = RandomRepl()
-
-
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/configs/common/cores/arm/ex5_big.py
b/configs/common/cores/arm/ex5_big.py
index f4ca047..96323f4 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -197,4 +197,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index bac6c73..544789b 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,6 +43,7 @@
from m5.proxy import *
from MemObject import MemObject
from Prefetcher import BasePrefetcher
+from ReplacementPolicies import *
from Tags import *
class BaseCache(MemObject):
@@ -74,7 +75,9 @@
prefetch_on_access = Param.Bool(False,
"Notify the hardware prefetcher on every access (not just
misses)")
- tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
+ tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
+ repl_policy = Param.BaseReplacementPolicy(LRURP(), "Replacement
policy")
+
sequential_access = Param.Bool(False,
"Whether to access tags and data sequentially")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 6f25323..2c7d9fb 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -52,8 +52,6 @@
#include "mem/cache/cache.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/tags/fa_lru.hh"
-#include "mem/cache/tags/lru.hh"
-#include "mem/cache/tags/random_repl.hh"
#include "sim/full_system.hh"
using namespace std;
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 44691c1..619b4d6 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -99,7 +99,7 @@
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick() will this block be accessable */
+ /** Which curTick() will this block be accessible */
Tick whenReady;
/**
@@ -117,8 +117,17 @@
/** holds the source requestor ID for this block. */
int srcMasterId;
+ /** Tick on which the block was inserted in the cache. */
Tick tickInserted;
+ /**
+ * Replacement policy data. May be a timestamp, re-reference distance,
+ * or other relevant information. As of now it is only a timestamp, but
+ * when more replacement policies are implemented, it should be
changed.
+ * @todo Change to accept other types of replacement data
+ */
+ Tick lastTouchTick;
+
protected:
/**
* Represents that the indicated thread context has a "lock" on
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 1821f18..426678a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -68,6 +68,7 @@
Cache::Cache(const CacheParams *p)
: BaseCache(p, p->system->cacheLineSize()),
tags(p->tags),
+ replPolicy(p->repl_policy),
prefetcher(p->prefetcher),
doFastWrites(true),
prefetchOnAccess(p->prefetch_on_access),
@@ -87,6 +88,7 @@
"MemSidePort");
tags->setCache(this);
+ replPolicy->setCache(this);
if (prefetcher)
prefetcher->setCache(this);
}
@@ -320,6 +322,10 @@
// that can modify its value.
blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
+ // Update replacement data of accessed block
+ if (blk)
+ replPolicy->touch(blk);
+
DPRINTF(Cache, "%s %s\n", pkt->print(),
blk ? "hit " + blk->print() : "miss");
@@ -396,6 +402,7 @@
return false;
}
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
blk->status = (BlkValid | BlkReadable);
if (pkt->isSecure()) {
@@ -456,6 +463,7 @@
return false;
}
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
blk->status = (BlkValid | BlkReadable);
if (pkt->isSecure()) {
@@ -1817,7 +1825,11 @@
CacheBlk*
Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
{
- CacheBlk *blk = tags->findVictim(addr);
+ // Get replacement candidates
+ ReplacementCandidates cands = tags->getCandidates(addr);
+
+ // Choose replacement victim from replacement candidates
+ CacheBlk *blk = replPolicy->getVictim(cands);
// It is valid to return nullptr if there is no victim
if (!blk)
@@ -1911,6 +1923,7 @@
is_secure ? "s" : "ns");
} else {
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
}
// we should never be overwriting a valid block
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4d840be..27bc7b2 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -59,6 +59,8 @@
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
+#include "mem/cache/replacement_policies/lru_rp.hh"
+#include "mem/cache/replacement_policies/random_rp.hh"
#include "mem/cache/tags/base.hh"
#include "params/Cache.hh"
#include "sim/eventq.hh"
@@ -190,6 +192,9 @@
/** Tag and data Storage */
BaseTags *tags;
+ /** Replacement policy */
+ BaseReplacementPolicy *replPolicy;
+
/** Prefetcher */
BasePrefetcher *prefetcher;
diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py
b/src/mem/cache/replacement_policies/ReplacementPolicies.py
new file mode 100644
index 0000000..f452628
--- /dev/null
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -0,0 +1,34 @@
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Daniel Carvalho
+
+from m5.params import *
+from m5.proxy import *
+from ClockedObject import ClockedObject
+
+class BaseReplacementPolicy(ClockedObject):
+ type = 'BaseReplacementPolicy'
+ abstract = True
+ cxx_header = "mem/cache/replacement_policies/base.hh"
+
+class LRURP(BaseReplacementPolicy):
+ type = 'LRURP'
+ cxx_class = 'LRURP'
+ cxx_header = "mem/cache/replacement_policies/lru_rp.hh"
+ timestamp_bits = Param.Unsigned(32,
+ "Number of bits used in timestamp representation for LRU")
+
+class RandomRP(BaseReplacementPolicy):
+ type = 'RandomRP'
+ cxx_class = 'RandomRP'
+ cxx_header = "mem/cache/replacement_policies/random_rp.hh"
diff --git a/src/mem/cache/replacement_policies/SConscript
b/src/mem/cache/replacement_policies/SConscript
new file mode 100644
index 0000000..eac5877
--- /dev/null
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -0,0 +1,37 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Daniel Carvalho
+
+Import('*')
+
+SimObject('ReplacementPolicies.py')
+
+Source('base.cc')
+Source('lru_rp.cc')
+Source('random_rp.cc')
diff --git a/src/mem/cache/replacement_policies/base.cc
b/src/mem/cache/replacement_policies/base.cc
new file mode 100644
index 0000000..0f68d68
--- /dev/null
+++ b/src/mem/cache/replacement_policies/base.cc
@@ -0,0 +1,52 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a common base class for cache replacement policy objects.
+ * In general replacement policies try to use invalid entries as victims,
+ * and if no such blocks exist the replacement policy is applied.
+ */
+
+#include "mem/cache/replacement_policies/base.hh"
+
+BaseReplacementPolicy::BaseReplacementPolicy(const Params *p)
+ : ClockedObject(p), cache(nullptr)
+{
+}
+
+void
+BaseReplacementPolicy::setCache(BaseCache *_cache)
+{
+ assert(!cache);
+ cache = _cache;
+}
+
+CacheBlk*
+BaseReplacementPolicy::forEachBlk(CacheBlkVictimVisitor &visitor,
+ ReplacementCandidates cands)
+{
+ // Visit all candidates to find victim
+ for (auto it = cands.begin(); it != cands.end(); ++it) {
+ // If block is very likely the best option, stop search
+ if (!visitor(**it))
+ break;
+ }
+
+ // Return the best victim
+ return visitor.getVictim();
+}
+
diff --git a/src/mem/cache/replacement_policies/base.hh
b/src/mem/cache/replacement_policies/base.hh
new file mode 100644
index 0000000..63cd52b
--- /dev/null
+++ b/src/mem/cache/replacement_policies/base.hh
@@ -0,0 +1,126 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
+
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/tags/base.hh" // For ReplacementCandidates
+#include "params/BaseReplacementPolicy.hh"
+#include "sim/clocked_object.hh"
+
+class BaseCache;
+
+/**
+ * Cache block visitor that searches for a replacement victim.
+ *
+ * Use with the forEachBlk method in the base replacement policy to find
+ * a suitable victim among the replacement candidates.
+ */
+class CacheBlkVictimVisitor : public CacheBlkVisitor
+{
+ protected:
+ /** Victim block chosen by the replacement policy. */
+ CacheBlk *victimBlk;
+
+ public:
+ /**
+ * Construct and initiliaze the visitor.
+ */
+ CacheBlkVictimVisitor() : victimBlk(nullptr) {}
+
+ /**
+ * The visiting/victim searching function to be implemented.
+ * It should update the victim block according to the replacement data.
+ *
+ * @return Keep search flag. False if should stop search.
+ */
+ virtual bool operator()(CacheBlk &blk) = 0;
+
+ /**
+ * Get the block to be replaced.
+ *
+ * @return The victim block.
+ */
+ CacheBlk* getVictim() const { return victimBlk; };
+};
+
+/**
+ * A common base class of cache replacement policy objects.
+ */
+class BaseReplacementPolicy : public ClockedObject
+{
+ protected:
+ BaseCache *cache; /** Pointer to the parent cache. */
+
+ /**
+ * Visit each block in the tag store and apply a visitor to the
+ * block.
+ *
+ * The visitor should be a function (or object that behaves like a
+ * function) that takes a cache block reference as its parameter
+ * and returns a bool. A visitor can request the traversal to be
+ * stopped by returning false, returning true causes it to be
+ * called for the next block in the tag store.
+ *
+ * @param visitor Visitor to call on each block.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return The replacement victim block.
+ */
+ CacheBlk* forEachBlk(CacheBlkVictimVisitor &visitor,
+ ReplacementCandidates cands);
+
+ public:
+ /**
+ * Convenience typedef.
+ */
+ typedef BaseReplacementPolicyParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ BaseReplacementPolicy(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ virtual ~BaseReplacementPolicy() {}
+
+ /**
+ * Set the parent cache back pointer.
+ *
+ * @param _cache Pointer to parent cache.
+ */
+ void setCache(BaseCache *_cache);
+
+ /**
+ * Touch a block to update its replacement data info.
+ *
+ * @param blk Cache block to be touched.
+ */
+ virtual void touch(CacheBlk *blk) { blk->isTouched = true; };
+
+ /**
+ * Find replacement victim among candidates.
+ *
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ virtual CacheBlk* getVictim(ReplacementCandidates cands) = 0;
+};
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
diff --git a/src/mem/cache/replacement_policies/lru_rp.cc
b/src/mem/cache/replacement_policies/lru_rp.cc
new file mode 100644
index 0000000..4ff69a2
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lru_rp.cc
@@ -0,0 +1,56 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/lru_rp.hh"
+
+#include "debug/CacheRepl.hh"
+
+LRURP::LRURP(const Params *p)
+ : BaseReplacementPolicy(p), tsBits(p->timestamp_bits)
+{
+}
+
+void
+LRURP::touch(CacheBlk *blk)
+{
+ // Inform block has been touched
+ blk->isTouched = true;
+
+ // Update last touch timestamp
+ blk->lastTouchTick = curTick();
+}
+
+CacheBlk*
+LRURP::getVictim(ReplacementCandidates cands)
+{
+ // There must be at least one replacement candidate
+ assert(cands.size() > 0);
+
+ // Use visitor to search for LRU victim
+ CacheBlkLRUVictimVisitor visitor;
+ CacheBlk* blk = forEachBlk(visitor, cands);
+
+ DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
+ blk->set, blk->way);
+
+ return blk;
+}
+
+LRURP*
+LRURPParams::create()
+{
+ return new LRURP(this);
+}
diff --git a/src/mem/cache/replacement_policies/lru_rp.hh
b/src/mem/cache/replacement_policies/lru_rp.hh
new file mode 100644
index 0000000..2ca1483
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -0,0 +1,98 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a Least Recently Used replacement policy.
+ * The victim is chosen using the timestamp. The timestamp may be true or
+ * pseudo, depending on the quantity of bits allocated for that.
+ */
+
+// TODO use parameter timestamp bits
+// TODO what should be done when timestamp overflows?
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
+
+#include "mem/cache/replacement_policies/base.hh"
+#include "params/LRURP.hh"
+
+class LRURP : public BaseReplacementPolicy
+{
+ protected:
+ /** Number of bits allocated for timestamp representation. */
+ const unsigned tsBits;
+
+ public:
+ /** Convenience typedef. */
+ typedef LRURPParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ LRURP(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ ~LRURP() {}
+
+ /**
+ * Touch a block to update its timestamp.
+ * @param blk Cache block to be touched.
+ */
+ void touch(CacheBlk *blk) override;
+
+ /**
+ * Find replacement victim using LRU timestamps.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ CacheBlk* getVictim(ReplacementCandidates cands) override;
+};
+
+/**
+ * Cache block visitor that determines searches for a replacement victim
+ * according to the LRU policy.
+ *
+ * Use with the forEachBlk method in the base replacement policy to find
+ * a suitable victim among the replacement candidates.
+ */
+class CacheBlkLRUVictimVisitor : public CacheBlkVictimVisitor
+{
+ public:
+ CacheBlkLRUVictimVisitor() : CacheBlkVictimVisitor() {}
+
+ bool operator()(CacheBlk &blk) override {
+ // Stop iteration if found an invalid block
+ /*if (!blk.isValid()) {
+ victimBlk = &blk;
+ return false;
+ } else {*/
+ // Update LRU block if necessary
+ if (!victimBlk or !blk.isValid() or
+ (blk.lastTouchTick < victimBlk->lastTouchTick)){
+ victimBlk = &blk;
+ }
+
+ // Continue searching for LRU block
+ return true;
+ //}
+ }
+};
+
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/random_rp.cc
b/src/mem/cache/replacement_policies/random_rp.cc
new file mode 100644
index 0000000..d7a9ce9
--- /dev/null
+++ b/src/mem/cache/replacement_policies/random_rp.cc
@@ -0,0 +1,46 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/random_rp.hh"
+
+#include "base/random.hh"
+#include "debug/CacheRepl.hh"
+
+RandomRP::RandomRP(const Params *p)
+ : BaseReplacementPolicy(p)
+{
+}
+
+CacheBlk*
+RandomRP::getVictim(ReplacementCandidates cands)
+{
+ // There must be at least one replacement candidate
+ assert(cands.size() > 0);
+
+ // Choose one of the candidates randomly
+ CacheBlk* blk = cands[random_mt.random<unsigned>(0, cands.size() - 1)];
+
+ DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
+ blk->set, blk->way);
+
+ return blk;
+}
+
+RandomRP*
+RandomRPParams::create()
+{
+ return new RandomRP(this);
+}
diff --git a/src/mem/cache/replacement_policies/random_rp.hh
b/src/mem/cache/replacement_policies/random_rp.hh
new file mode 100644
index 0000000..004b28f
--- /dev/null
+++ b/src/mem/cache/replacement_policies/random_rp.hh
@@ -0,0 +1,59 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a random replacement policy.
+ * The victim is chosen at random, regardless if there are invalid entries.
+ */
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
+
+#include "mem/cache/replacement_policies/base.hh"
+#include "params/RandomRP.hh"
+
+class RandomRP : public BaseReplacementPolicy
+{
+ public:
+ /** Convenience typedef. */
+ typedef RandomRPParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ RandomRP(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ ~RandomRP() {}
+
+ /**
+ * Touch a block. Does not do anything.
+ * @param blk Cache block to be touched.
+ */
+ void touch(CacheBlk *blk) override {}
+
+ /**
+ * Find replacement victim at random.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ CacheBlk* getVictim(ReplacementCandidates cands) override;
+};
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 1412286..9758b56 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -34,6 +34,4 @@
Source('base.cc')
Source('base_set_assoc.cc')
-Source('lru.cc')
-Source('random_repl.cc')
Source('fa_lru.cc')
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index b19010f..231f81a 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -66,20 +66,9 @@
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
- abstract = True
cxx_header = "mem/cache/tags/base_set_assoc.hh"
assoc = Param.Int(Parent.assoc, "associativity")
-class LRU(BaseSetAssoc):
- type = 'LRU'
- cxx_class = 'LRU'
- cxx_header = "mem/cache/tags/lru.hh"
-
-class RandomRepl(BaseSetAssoc):
- type = 'RandomRepl'
- cxx_class = 'RandomRepl'
- cxx_header = "mem/cache/tags/random_repl.hh"
-
class FALRU(BaseTags):
type = 'FALRU'
cxx_class = 'FALRU'
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 2c528a9..fef4c38 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -60,6 +60,11 @@
class BaseCache;
/**
+ * Replacement candidates as chosen by the indexing policy.
+ */
+typedef std::vector<CacheBlk*> ReplacementCandidates;
+
+/**
* A common base class of Cache tagstore objects.
*/
class BaseTags : public ClockedObject
@@ -246,7 +251,7 @@
virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0;
- virtual CacheBlk* findVictim(Addr addr) = 0;
+ virtual ReplacementCandidates getCandidates(Addr addr) = 0;
virtual int extractSet(Addr addr) const = 0;
diff --git a/src/mem/cache/tags/base_set_assoc.cc
b/src/mem/cache/tags/base_set_assoc.cc
index cf647ac..34a9c23 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -193,3 +193,10 @@
}
}
}
+
+BaseSetAssoc *
+BaseSetAssocParams::create()
+{
+ return new BaseSetAssoc(this);
+}
+
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index ef4c68b..1673e53 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -63,15 +63,9 @@
* A BaseSetAssoc cache tag store.
* @sa \ref gem5MemorySystem "gem5 Memory System"
*
- * The BaseSetAssoc tags provide a base, as well as the functionality
- * common to any set associative tags. Any derived class must implement
- * the methods related to the specifics of the actual replacment policy.
- * These are:
- *
- * BlkType* accessBlock();
- * BlkType* findVictim();
- * void insertBlock();
- * void invalidate();
+ * The BaseSetAssoc placement policy divides the cache into s sets of w
+ * cache lines (ways). A cache line is mapped onto a set, and can be placed
+ * into any of the ways of this set.
*/
class BaseSetAssoc : public BaseTags
{
@@ -147,10 +141,9 @@
}
/**
- * Access block and update replacement data. May not succeed, in which
case
- * nullptr is returned. This has all the implications of a cache
- * access and should only be used as such. Returns the access latency
as a
- * side effect.
+ * Access block. May not succeed, in which case nullptr is returned.
This
+ * has all the implications of a cache access and should only be used
as
+ * such. Returns the access latency as a side effect.
* @param addr The address to find.
* @param is_secure True if the target memory space is secure.
* @param lat The access latency.
@@ -205,25 +198,24 @@
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
- * Find an invalid block to evict for the address provided.
- * If there are no invalid blocks, this will return the block
- * in the least-recently-used position.
- * @param addr The addr to a find a replacement candidate for.
- * @return The candidate block.
+ * Find all candidates for replacement. Returns blocks in all ways
+ * belonging to the set of the address.
+ * @param addr The addr to a find replacement candidates for.
+ * @return The replacement candidates.
*/
- CacheBlk* findVictim(Addr addr) override
+ ReplacementCandidates getCandidates(Addr addr) override
{
- BlkType *blk = nullptr;
+ ReplacementCandidates cands;
+
+ // Get working set
int set = extractSet(addr);
- // prefer to evict an invalid block
+ // Get all entries in the working set
for (int i = 0; i < allocAssoc; ++i) {
- blk = sets[set].blks[i];
- if (!blk->isValid())
- break;
+ cands.push_back(sets[set].blks[i]);
}
- return blk;
+ return cands;
}
/**
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index dfd4c40..7ffd9a1 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -245,9 +245,11 @@
return &blks[way];
}
-CacheBlk*
-FALRU::findVictim(Addr addr)
+ReplacementCandidates
+FALRU::getCandidates(Addr addr)
{
+ ReplacementCandidates cands;
+
FALRUBlk * blk = tail;
assert(blk->inCache == 0);
moveToHead(blk);
@@ -264,7 +266,12 @@
}
}
//assert(check());
- return blk;
+
+ // FALRU is a specialization that does not use the ReplacementPolicy
+ // classes to make decisions regarding which block to evict
+ cands.push_back(blk);
+
+ return cands;
}
void
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index a266fb5..2ebfdcd 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -204,11 +204,11 @@
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
- * Find a replacement block for the address provided.
- * @param pkt The request to a find a replacement candidate for.
- * @return The block to place the replacement in.
+ * Find all candidates for replacement.
+ * @param pkt The request to a find replacement candidates for.
+ * @return The replacement candidates.
*/
- CacheBlk* findVictim(Addr addr) override;
+ ReplacementCandidates getCandidates(Addr addr) override;
void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
deleted file mode 100644
index 5fc48b9..0000000
--- a/src/mem/cache/tags/lru.cc
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2012-2013 ARM Limited
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * Definitions of a LRU tag store.
- */
-
-#include "mem/cache/tags/lru.hh"
-
-#include "debug/CacheRepl.hh"
-#include "mem/cache/base.hh"
-
-LRU::LRU(const Params *p)
- : BaseSetAssoc(p)
-{
-}
-
-CacheBlk*
-LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
-{
- CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat);
-
- if (blk != nullptr) {
- // move this block to head of the MRU list
- sets[blk->set].moveToHead(blk);
- DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n",
- blk->set, regenerateBlkAddr(blk->tag, blk->set),
- is_secure ? "s" : "ns");
- }
-
- return blk;
-}
-
-CacheBlk*
-LRU::findVictim(Addr addr)
-{
- int set = extractSet(addr);
- // grab a replacement candidate
- BlkType *blk = nullptr;
- for (int i = assoc - 1; i >= 0; i--) {
- BlkType *b = sets[set].blks[i];
- if (b->way < allocAssoc) {
- blk = b;
- break;
- }
- }
- assert(!blk || blk->way < allocAssoc);
-
- if (blk && blk->isValid()) {
- DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
- set, regenerateBlkAddr(blk->tag, set));
- }
-
- return blk;
-}
-
-void
-LRU::insertBlock(PacketPtr pkt, BlkType *blk)
-{
- BaseSetAssoc::insertBlock(pkt, blk);
-
- int set = extractSet(pkt->getAddr());
- sets[set].moveToHead(blk);
-}
-
-void
-LRU::invalidate(CacheBlk *blk)
-{
- BaseSetAssoc::invalidate(blk);
-
- // should be evicted before valid blocks
- int set = blk->set;
- sets[set].moveToTail(blk);
-}
-
-LRU*
-LRUParams::create()
-{
- return new LRU(this);
-}
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
deleted file mode 100644
index d38b94e..0000000
--- a/src/mem/cache/tags/lru.hh
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2012-2013 ARM Limited
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * Declaration of a LRU tag store.
- * The LRU tags guarantee that the true least-recently-used way in
- * a set will always be evicted.
- */
-
-#ifndef __MEM_CACHE_TAGS_LRU_HH__
-#define __MEM_CACHE_TAGS_LRU_HH__
-
-#include "mem/cache/tags/base_set_assoc.hh"
-#include "params/LRU.hh"
-
-class LRU : public BaseSetAssoc
-{
- public:
- /** Convenience typedef. */
- typedef LRUParams Params;
-
- /**
- * Construct and initialize this tag store.
- */
- LRU(const Params *p);
-
- /**
- * Destructor
- */
- ~LRU() {}
-
- CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
- CacheBlk* findVictim(Addr addr);
- void insertBlock(PacketPtr pkt, BlkType *blk);
- void invalidate(CacheBlk *blk);
-};
-
-#endif // __MEM_CACHE_TAGS_LRU_HH__
diff --git a/src/mem/cache/tags/random_repl.cc
b/src/mem/cache/tags/random_repl.cc
deleted file mode 100644
index ab51f64..0000000
--- a/src/mem/cache/tags/random_repl.cc
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2014 The Regents of The University of Michigan
- * Copyright (c) 2016 ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
- */
-
-/**
- * @file
- * Definitions of a random replacement tag store.
- */
-
-#include "mem/cache/tags/random_repl.hh"
-
-#include "base/random.hh"
-#include "debug/CacheRepl.hh"
-#include "mem/cache/base.hh"
-
-RandomRepl::RandomRepl(const Params *p)
- : BaseSetAssoc(p)
-
-{
-}
-
-CacheBlk*
-RandomRepl::accessBlock(Addr addr, bool is_secure, Cycles &lat)
-{
- return BaseSetAssoc::accessBlock(addr, is_secure, lat);
-}
-
-CacheBlk*
-RandomRepl::findVictim(Addr addr)
-{
- CacheBlk *blk = BaseSetAssoc::findVictim(addr);
- unsigned set = extractSet(addr);
-
- // if all blocks are valid, pick a replacement at random
- if (blk && blk->isValid()) {
- // find a random index within the bounds of the set
- int idx = random_mt.random<int>(0, assoc - 1);
- blk = sets[set].blks[idx];
- // Enforce allocation limit
- while (blk->way >= allocAssoc) {
- idx = (idx + 1) % assoc;
- blk = sets[set].blks[idx];
- }
-
- assert(idx < assoc);
- assert(idx >= 0);
- assert(blk->way < allocAssoc);
-
- DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
- blk->set, regenerateBlkAddr(blk->tag, blk->set));
- }
-
- return blk;
-}
-
-void
-RandomRepl::insertBlock(PacketPtr pkt, BlkType *blk)
-{
- BaseSetAssoc::insertBlock(pkt, blk);
-}
-
-void
-RandomRepl::invalidate(CacheBlk *blk)
-{
- BaseSetAssoc::invalidate(blk);
-}
-
-RandomRepl*
-RandomReplParams::create()
-{
- return new RandomRepl(this);
-}
diff --git a/src/mem/cache/tags/random_repl.hh
b/src/mem/cache/tags/random_repl.hh
deleted file mode 100644
index 8f08a70..0000000
--- a/src/mem/cache/tags/random_repl.hh
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
- */
-
-/**
- * @file
- * Declaration of a random replacement tag store.
- * The RandomRepl tags first try to evict an invalid
- * block. If no invalid blocks are found, a candidate
- * for eviction is found at random.
- */
-
-#ifndef __MEM_CACHE_TAGS_RANDOM_REPL_HH__
-#define __MEM_CACHE_TAGS_RANDOM_REPL_HH__
-
-#include "mem/cache/tags/base_set_assoc.hh"
-#include "params/RandomRepl.hh"
-
-class RandomRepl : public BaseSetAssoc
-{
- public:
- /** Convenience typedef. */
- typedef RandomReplParams Params;
-
- /**
- * Construct and initiliaze this tag store.
- */
- RandomRepl(const Params *p);
-
- /**
- * Destructor
- */
- ~RandomRepl() {}
-
- CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
- CacheBlk* findVictim(Addr addr);
- void insertBlock(PacketPtr pkt, BlkType *blk);
- void invalidate(CacheBlk *blk);
-};
-
-#endif // __MEM_CACHE_TAGS_RANDOM_REPL_HH__
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index ad65ef7..50885fb 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -858,6 +858,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -901,7 +902,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -916,6 +917,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1697,6 +1708,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1740,7 +1752,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1755,6 +1767,16 @@
size=1048576
tag_latency=12
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 1c09997..b16d8c9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -769,6 +769,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -812,7 +813,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -827,6 +828,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1519,6 +1530,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1562,7 +1574,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1577,6 +1589,16 @@
size=1048576
tag_latency=12
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index bcf1aa1..8cbea51 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -837,6 +837,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -879,7 +880,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -893,6 +894,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1653,6 +1664,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1695,7 +1707,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1709,6 +1721,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index d65c440..8a12ce2 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -740,6 +740,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -782,7 +783,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -796,6 +797,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1459,6 +1470,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1501,7 +1513,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1515,6 +1527,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 4ef1d1b..67662fb 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -403,6 +403,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -445,7 +446,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -459,6 +460,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -785,6 +796,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -827,7 +839,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -841,6 +853,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 9e59e49..5ec3d6c 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -399,6 +399,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -441,7 +442,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -455,6 +456,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -777,6 +788,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -819,7 +831,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -833,6 +845,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index e061f70..b9dffa5 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index e92ae69..0d17d21 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 2c21341..b7b65f9 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 721f1a5..de83a55 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 609dcfe..01d142c 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 5da6802..0a21511 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 87b4a60..6d789f0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 01bc995..6a950c6 100644
---
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -403,6 +403,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -445,7 +446,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -459,6 +460,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -785,6 +796,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -827,7 +839,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -841,6 +853,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 4448abd..14f6ddd 100644
---
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -400,6 +400,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -443,7 +444,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -458,6 +459,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -781,6 +792,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -824,7 +836,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -839,6 +851,17 @@
size=1048576
tag_latency=12
+
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 72771fa..43a1cc4 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
--
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Gerrit-Change-Number: 8501
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <***@yahoo.com.br>
https://gem5-review.googlesource.com/8501
Change subject: mem-cache: Split array indexing and replacement policies.
......................................................................
mem-cache: Split array indexing and replacement policies.
Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:
- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.
For this reason, they were split into different classes. Advantages:
- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes
As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).
Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
---
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
A src/mem/cache/replacement_policies/ReplacementPolicies.py
A src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/base.cc
A src/mem/cache/replacement_policies/base.hh
A src/mem/cache/replacement_policies/lru_rp.cc
A src/mem/cache/replacement_policies/lru_rp.hh
A src/mem/cache/replacement_policies/random_rp.cc
A src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/tags/SConscript
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
D src/mem/cache/tags/lru.cc
D src/mem/cache/tags/lru.hh
D src/mem/cache/tags/random_repl.cc
D src/mem/cache/tags/random_repl.hh
M tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
M tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
M
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
M
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
M tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
M tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
M tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
M tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
M tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
M tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
M tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
M
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
M
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
M tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
43 files changed, 880 insertions(+), 444 deletions(-)
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py
b/configs/common/cores/arm/O3_ARM_v7a.py
index fde4d3c..b0ba128 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -201,4 +201,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/configs/common/cores/arm/ex5_LITTLE.py
b/configs/common/cores/arm/ex5_LITTLE.py
index a866b16..1ae0f16 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -145,6 +145,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=1, latency = 1)
- tags = RandomRepl()
-
-
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/configs/common/cores/arm/ex5_big.py
b/configs/common/cores/arm/ex5_big.py
index f4ca047..96323f4 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -197,4 +197,5 @@
clusivity = 'mostly_excl'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
+ tags = BaseSetAssoc()
+ repl_policy = RandomRP()
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index bac6c73..544789b 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,6 +43,7 @@
from m5.proxy import *
from MemObject import MemObject
from Prefetcher import BasePrefetcher
+from ReplacementPolicies import *
from Tags import *
class BaseCache(MemObject):
@@ -74,7 +75,9 @@
prefetch_on_access = Param.Bool(False,
"Notify the hardware prefetcher on every access (not just
misses)")
- tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
+ tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
+ repl_policy = Param.BaseReplacementPolicy(LRURP(), "Replacement
policy")
+
sequential_access = Param.Bool(False,
"Whether to access tags and data sequentially")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 6f25323..2c7d9fb 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -52,8 +52,6 @@
#include "mem/cache/cache.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/tags/fa_lru.hh"
-#include "mem/cache/tags/lru.hh"
-#include "mem/cache/tags/random_repl.hh"
#include "sim/full_system.hh"
using namespace std;
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 44691c1..619b4d6 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -99,7 +99,7 @@
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick() will this block be accessable */
+ /** Which curTick() will this block be accessible */
Tick whenReady;
/**
@@ -117,8 +117,17 @@
/** holds the source requestor ID for this block. */
int srcMasterId;
+ /** Tick on which the block was inserted in the cache. */
Tick tickInserted;
+ /**
+ * Replacement policy data. May be a timestamp, re-reference distance,
+ * or other relevant information. As of now it is only a timestamp, but
+ * when more replacement policies are implemented, it should be
changed.
+ * @todo Change to accept other types of replacement data
+ */
+ Tick lastTouchTick;
+
protected:
/**
* Represents that the indicated thread context has a "lock" on
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 1821f18..426678a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -68,6 +68,7 @@
Cache::Cache(const CacheParams *p)
: BaseCache(p, p->system->cacheLineSize()),
tags(p->tags),
+ replPolicy(p->repl_policy),
prefetcher(p->prefetcher),
doFastWrites(true),
prefetchOnAccess(p->prefetch_on_access),
@@ -87,6 +88,7 @@
"MemSidePort");
tags->setCache(this);
+ replPolicy->setCache(this);
if (prefetcher)
prefetcher->setCache(this);
}
@@ -320,6 +322,10 @@
// that can modify its value.
blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
+ // Update replacement data of accessed block
+ if (blk)
+ replPolicy->touch(blk);
+
DPRINTF(Cache, "%s %s\n", pkt->print(),
blk ? "hit " + blk->print() : "miss");
@@ -396,6 +402,7 @@
return false;
}
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
blk->status = (BlkValid | BlkReadable);
if (pkt->isSecure()) {
@@ -456,6 +463,7 @@
return false;
}
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
blk->status = (BlkValid | BlkReadable);
if (pkt->isSecure()) {
@@ -1817,7 +1825,11 @@
CacheBlk*
Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
{
- CacheBlk *blk = tags->findVictim(addr);
+ // Get replacement candidates
+ ReplacementCandidates cands = tags->getCandidates(addr);
+
+ // Choose replacement victim from replacement candidates
+ CacheBlk *blk = replPolicy->getVictim(cands);
// It is valid to return nullptr if there is no victim
if (!blk)
@@ -1911,6 +1923,7 @@
is_secure ? "s" : "ns");
} else {
tags->insertBlock(pkt, blk);
+ replPolicy->touch(blk);
}
// we should never be overwriting a valid block
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4d840be..27bc7b2 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -59,6 +59,8 @@
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
+#include "mem/cache/replacement_policies/lru_rp.hh"
+#include "mem/cache/replacement_policies/random_rp.hh"
#include "mem/cache/tags/base.hh"
#include "params/Cache.hh"
#include "sim/eventq.hh"
@@ -190,6 +192,9 @@
/** Tag and data Storage */
BaseTags *tags;
+ /** Replacement policy */
+ BaseReplacementPolicy *replPolicy;
+
/** Prefetcher */
BasePrefetcher *prefetcher;
diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py
b/src/mem/cache/replacement_policies/ReplacementPolicies.py
new file mode 100644
index 0000000..f452628
--- /dev/null
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -0,0 +1,34 @@
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Daniel Carvalho
+
+from m5.params import *
+from m5.proxy import *
+from ClockedObject import ClockedObject
+
+class BaseReplacementPolicy(ClockedObject):
+ type = 'BaseReplacementPolicy'
+ abstract = True
+ cxx_header = "mem/cache/replacement_policies/base.hh"
+
+class LRURP(BaseReplacementPolicy):
+ type = 'LRURP'
+ cxx_class = 'LRURP'
+ cxx_header = "mem/cache/replacement_policies/lru_rp.hh"
+ timestamp_bits = Param.Unsigned(32,
+ "Number of bits used in timestamp representation for LRU")
+
+class RandomRP(BaseReplacementPolicy):
+ type = 'RandomRP'
+ cxx_class = 'RandomRP'
+ cxx_header = "mem/cache/replacement_policies/random_rp.hh"
diff --git a/src/mem/cache/replacement_policies/SConscript
b/src/mem/cache/replacement_policies/SConscript
new file mode 100644
index 0000000..eac5877
--- /dev/null
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -0,0 +1,37 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Daniel Carvalho
+
+Import('*')
+
+SimObject('ReplacementPolicies.py')
+
+Source('base.cc')
+Source('lru_rp.cc')
+Source('random_rp.cc')
diff --git a/src/mem/cache/replacement_policies/base.cc
b/src/mem/cache/replacement_policies/base.cc
new file mode 100644
index 0000000..0f68d68
--- /dev/null
+++ b/src/mem/cache/replacement_policies/base.cc
@@ -0,0 +1,52 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a common base class for cache replacement policy objects.
+ * In general replacement policies try to use invalid entries as victims,
+ * and if no such blocks exist the replacement policy is applied.
+ */
+
+#include "mem/cache/replacement_policies/base.hh"
+
+BaseReplacementPolicy::BaseReplacementPolicy(const Params *p)
+ : ClockedObject(p), cache(nullptr)
+{
+}
+
+void
+BaseReplacementPolicy::setCache(BaseCache *_cache)
+{
+ assert(!cache);
+ cache = _cache;
+}
+
+CacheBlk*
+BaseReplacementPolicy::forEachBlk(CacheBlkVictimVisitor &visitor,
+ ReplacementCandidates cands)
+{
+ // Visit all candidates to find victim
+ for (auto it = cands.begin(); it != cands.end(); ++it) {
+ // If block is very likely the best option, stop search
+ if (!visitor(**it))
+ break;
+ }
+
+ // Return the best victim
+ return visitor.getVictim();
+}
+
diff --git a/src/mem/cache/replacement_policies/base.hh
b/src/mem/cache/replacement_policies/base.hh
new file mode 100644
index 0000000..63cd52b
--- /dev/null
+++ b/src/mem/cache/replacement_policies/base.hh
@@ -0,0 +1,126 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
+
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/tags/base.hh" // For ReplacementCandidates
+#include "params/BaseReplacementPolicy.hh"
+#include "sim/clocked_object.hh"
+
+class BaseCache;
+
+/**
+ * Cache block visitor that searches for a replacement victim.
+ *
+ * Use with the forEachBlk method in the base replacement policy to find
+ * a suitable victim among the replacement candidates.
+ */
+class CacheBlkVictimVisitor : public CacheBlkVisitor
+{
+ protected:
+ /** Victim block chosen by the replacement policy. */
+ CacheBlk *victimBlk;
+
+ public:
+ /**
+ * Construct and initiliaze the visitor.
+ */
+ CacheBlkVictimVisitor() : victimBlk(nullptr) {}
+
+ /**
+ * The visiting/victim searching function to be implemented.
+ * It should update the victim block according to the replacement data.
+ *
+ * @return Keep search flag. False if should stop search.
+ */
+ virtual bool operator()(CacheBlk &blk) = 0;
+
+ /**
+ * Get the block to be replaced.
+ *
+ * @return The victim block.
+ */
+ CacheBlk* getVictim() const { return victimBlk; };
+};
+
+/**
+ * A common base class of cache replacement policy objects.
+ */
+class BaseReplacementPolicy : public ClockedObject
+{
+ protected:
+ BaseCache *cache; /** Pointer to the parent cache. */
+
+ /**
+ * Visit each block in the tag store and apply a visitor to the
+ * block.
+ *
+ * The visitor should be a function (or object that behaves like a
+ * function) that takes a cache block reference as its parameter
+ * and returns a bool. A visitor can request the traversal to be
+ * stopped by returning false, returning true causes it to be
+ * called for the next block in the tag store.
+ *
+ * @param visitor Visitor to call on each block.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return The replacement victim block.
+ */
+ CacheBlk* forEachBlk(CacheBlkVictimVisitor &visitor,
+ ReplacementCandidates cands);
+
+ public:
+ /**
+ * Convenience typedef.
+ */
+ typedef BaseReplacementPolicyParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ BaseReplacementPolicy(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ virtual ~BaseReplacementPolicy() {}
+
+ /**
+ * Set the parent cache back pointer.
+ *
+ * @param _cache Pointer to parent cache.
+ */
+ void setCache(BaseCache *_cache);
+
+ /**
+ * Touch a block to update its replacement data info.
+ *
+ * @param blk Cache block to be touched.
+ */
+ virtual void touch(CacheBlk *blk) { blk->isTouched = true; };
+
+ /**
+ * Find replacement victim among candidates.
+ *
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ virtual CacheBlk* getVictim(ReplacementCandidates cands) = 0;
+};
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
diff --git a/src/mem/cache/replacement_policies/lru_rp.cc
b/src/mem/cache/replacement_policies/lru_rp.cc
new file mode 100644
index 0000000..4ff69a2
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lru_rp.cc
@@ -0,0 +1,56 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/lru_rp.hh"
+
+#include "debug/CacheRepl.hh"
+
+LRURP::LRURP(const Params *p)
+ : BaseReplacementPolicy(p), tsBits(p->timestamp_bits)
+{
+}
+
+void
+LRURP::touch(CacheBlk *blk)
+{
+ // Inform block has been touched
+ blk->isTouched = true;
+
+ // Update last touch timestamp
+ blk->lastTouchTick = curTick();
+}
+
+CacheBlk*
+LRURP::getVictim(ReplacementCandidates cands)
+{
+ // There must be at least one replacement candidate
+ assert(cands.size() > 0);
+
+ // Use visitor to search for LRU victim
+ CacheBlkLRUVictimVisitor visitor;
+ CacheBlk* blk = forEachBlk(visitor, cands);
+
+ DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
+ blk->set, blk->way);
+
+ return blk;
+}
+
+LRURP*
+LRURPParams::create()
+{
+ return new LRURP(this);
+}
diff --git a/src/mem/cache/replacement_policies/lru_rp.hh
b/src/mem/cache/replacement_policies/lru_rp.hh
new file mode 100644
index 0000000..2ca1483
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -0,0 +1,98 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a Least Recently Used replacement policy.
+ * The victim is chosen using the timestamp. The timestamp may be true or
+ * pseudo, depending on the quantity of bits allocated for that.
+ */
+
+// TODO use parameter timestamp bits
+// TODO what should be done when timestamp overflows?
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
+
+#include "mem/cache/replacement_policies/base.hh"
+#include "params/LRURP.hh"
+
+class LRURP : public BaseReplacementPolicy
+{
+ protected:
+ /** Number of bits allocated for timestamp representation. */
+ const unsigned tsBits;
+
+ public:
+ /** Convenience typedef. */
+ typedef LRURPParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ LRURP(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ ~LRURP() {}
+
+ /**
+ * Touch a block to update its timestamp.
+ * @param blk Cache block to be touched.
+ */
+ void touch(CacheBlk *blk) override;
+
+ /**
+ * Find replacement victim using LRU timestamps.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ CacheBlk* getVictim(ReplacementCandidates cands) override;
+};
+
+/**
+ * Cache block visitor that determines searches for a replacement victim
+ * according to the LRU policy.
+ *
+ * Use with the forEachBlk method in the base replacement policy to find
+ * a suitable victim among the replacement candidates.
+ */
+class CacheBlkLRUVictimVisitor : public CacheBlkVictimVisitor
+{
+ public:
+ CacheBlkLRUVictimVisitor() : CacheBlkVictimVisitor() {}
+
+ bool operator()(CacheBlk &blk) override {
+ // Stop iteration if found an invalid block
+ /*if (!blk.isValid()) {
+ victimBlk = &blk;
+ return false;
+ } else {*/
+ // Update LRU block if necessary
+ if (!victimBlk or !blk.isValid() or
+ (blk.lastTouchTick < victimBlk->lastTouchTick)){
+ victimBlk = &blk;
+ }
+
+ // Continue searching for LRU block
+ return true;
+ //}
+ }
+};
+
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/random_rp.cc
b/src/mem/cache/replacement_policies/random_rp.cc
new file mode 100644
index 0000000..d7a9ce9
--- /dev/null
+++ b/src/mem/cache/replacement_policies/random_rp.cc
@@ -0,0 +1,46 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/random_rp.hh"
+
+#include "base/random.hh"
+#include "debug/CacheRepl.hh"
+
+RandomRP::RandomRP(const Params *p)
+ : BaseReplacementPolicy(p)
+{
+}
+
+CacheBlk*
+RandomRP::getVictim(ReplacementCandidates cands)
+{
+ // There must be at least one replacement candidate
+ assert(cands.size() > 0);
+
+ // Choose one of the candidates randomly
+ CacheBlk* blk = cands[random_mt.random<unsigned>(0, cands.size() - 1)];
+
+ DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
+ blk->set, blk->way);
+
+ return blk;
+}
+
+RandomRP*
+RandomRPParams::create()
+{
+ return new RandomRP(this);
+}
diff --git a/src/mem/cache/replacement_policies/random_rp.hh
b/src/mem/cache/replacement_policies/random_rp.hh
new file mode 100644
index 0000000..004b28f
--- /dev/null
+++ b/src/mem/cache/replacement_policies/random_rp.hh
@@ -0,0 +1,59 @@
+/**
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+/**
+ * @file
+ * Declaration of a random replacement policy.
+ * The victim is chosen at random, regardless if there are invalid entries.
+ */
+
+#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
+#define __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
+
+#include "mem/cache/replacement_policies/base.hh"
+#include "params/RandomRP.hh"
+
+class RandomRP : public BaseReplacementPolicy
+{
+ public:
+ /** Convenience typedef. */
+ typedef RandomRPParams Params;
+
+ /**
+ * Construct and initiliaze this replacement policy.
+ */
+ RandomRP(const Params *p);
+
+ /**
+ * Destructor.
+ */
+ ~RandomRP() {}
+
+ /**
+ * Touch a block. Does not do anything.
+ * @param blk Cache block to be touched.
+ */
+ void touch(CacheBlk *blk) override {}
+
+ /**
+ * Find replacement victim at random.
+ * @param cands Replacement candidates, selected by indexing policy.
+ * @return Cache block to be replaced.
+ */
+ CacheBlk* getVictim(ReplacementCandidates cands) override;
+};
+
+#endif // __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 1412286..9758b56 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -34,6 +34,4 @@
Source('base.cc')
Source('base_set_assoc.cc')
-Source('lru.cc')
-Source('random_repl.cc')
Source('fa_lru.cc')
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index b19010f..231f81a 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -66,20 +66,9 @@
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
- abstract = True
cxx_header = "mem/cache/tags/base_set_assoc.hh"
assoc = Param.Int(Parent.assoc, "associativity")
-class LRU(BaseSetAssoc):
- type = 'LRU'
- cxx_class = 'LRU'
- cxx_header = "mem/cache/tags/lru.hh"
-
-class RandomRepl(BaseSetAssoc):
- type = 'RandomRepl'
- cxx_class = 'RandomRepl'
- cxx_header = "mem/cache/tags/random_repl.hh"
-
class FALRU(BaseTags):
type = 'FALRU'
cxx_class = 'FALRU'
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 2c528a9..fef4c38 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -60,6 +60,11 @@
class BaseCache;
/**
+ * Replacement candidates as chosen by the indexing policy.
+ */
+typedef std::vector<CacheBlk*> ReplacementCandidates;
+
+/**
* A common base class of Cache tagstore objects.
*/
class BaseTags : public ClockedObject
@@ -246,7 +251,7 @@
virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0;
- virtual CacheBlk* findVictim(Addr addr) = 0;
+ virtual ReplacementCandidates getCandidates(Addr addr) = 0;
virtual int extractSet(Addr addr) const = 0;
diff --git a/src/mem/cache/tags/base_set_assoc.cc
b/src/mem/cache/tags/base_set_assoc.cc
index cf647ac..34a9c23 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -193,3 +193,10 @@
}
}
}
+
+BaseSetAssoc *
+BaseSetAssocParams::create()
+{
+ return new BaseSetAssoc(this);
+}
+
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index ef4c68b..1673e53 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -63,15 +63,9 @@
* A BaseSetAssoc cache tag store.
* @sa \ref gem5MemorySystem "gem5 Memory System"
*
- * The BaseSetAssoc tags provide a base, as well as the functionality
- * common to any set associative tags. Any derived class must implement
- * the methods related to the specifics of the actual replacment policy.
- * These are:
- *
- * BlkType* accessBlock();
- * BlkType* findVictim();
- * void insertBlock();
- * void invalidate();
+ * The BaseSetAssoc placement policy divides the cache into s sets of w
+ * cache lines (ways). A cache line is mapped onto a set, and can be placed
+ * into any of the ways of this set.
*/
class BaseSetAssoc : public BaseTags
{
@@ -147,10 +141,9 @@
}
/**
- * Access block and update replacement data. May not succeed, in which
case
- * nullptr is returned. This has all the implications of a cache
- * access and should only be used as such. Returns the access latency
as a
- * side effect.
+ * Access block. May not succeed, in which case nullptr is returned.
This
+ * has all the implications of a cache access and should only be used
as
+ * such. Returns the access latency as a side effect.
* @param addr The address to find.
* @param is_secure True if the target memory space is secure.
* @param lat The access latency.
@@ -205,25 +198,24 @@
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
- * Find an invalid block to evict for the address provided.
- * If there are no invalid blocks, this will return the block
- * in the least-recently-used position.
- * @param addr The addr to a find a replacement candidate for.
- * @return The candidate block.
+ * Find all candidates for replacement. Returns blocks in all ways
+ * belonging to the set of the address.
+ * @param addr The addr to a find replacement candidates for.
+ * @return The replacement candidates.
*/
- CacheBlk* findVictim(Addr addr) override
+ ReplacementCandidates getCandidates(Addr addr) override
{
- BlkType *blk = nullptr;
+ ReplacementCandidates cands;
+
+ // Get working set
int set = extractSet(addr);
- // prefer to evict an invalid block
+ // Get all entries in the working set
for (int i = 0; i < allocAssoc; ++i) {
- blk = sets[set].blks[i];
- if (!blk->isValid())
- break;
+ cands.push_back(sets[set].blks[i]);
}
- return blk;
+ return cands;
}
/**
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index dfd4c40..7ffd9a1 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -245,9 +245,11 @@
return &blks[way];
}
-CacheBlk*
-FALRU::findVictim(Addr addr)
+ReplacementCandidates
+FALRU::getCandidates(Addr addr)
{
+ ReplacementCandidates cands;
+
FALRUBlk * blk = tail;
assert(blk->inCache == 0);
moveToHead(blk);
@@ -264,7 +266,12 @@
}
}
//assert(check());
- return blk;
+
+ // FALRU is a specialization that does not use the ReplacementPolicy
+ // classes to make decisions regarding which block to evict
+ cands.push_back(blk);
+
+ return cands;
}
void
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index a266fb5..2ebfdcd 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -204,11 +204,11 @@
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
- * Find a replacement block for the address provided.
- * @param pkt The request to a find a replacement candidate for.
- * @return The block to place the replacement in.
+ * Find all candidates for replacement.
+ * @param pkt The request to a find replacement candidates for.
+ * @return The replacement candidates.
*/
- CacheBlk* findVictim(Addr addr) override;
+ ReplacementCandidates getCandidates(Addr addr) override;
void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
deleted file mode 100644
index 5fc48b9..0000000
--- a/src/mem/cache/tags/lru.cc
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2012-2013 ARM Limited
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * Definitions of a LRU tag store.
- */
-
-#include "mem/cache/tags/lru.hh"
-
-#include "debug/CacheRepl.hh"
-#include "mem/cache/base.hh"
-
-LRU::LRU(const Params *p)
- : BaseSetAssoc(p)
-{
-}
-
-CacheBlk*
-LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
-{
- CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat);
-
- if (blk != nullptr) {
- // move this block to head of the MRU list
- sets[blk->set].moveToHead(blk);
- DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n",
- blk->set, regenerateBlkAddr(blk->tag, blk->set),
- is_secure ? "s" : "ns");
- }
-
- return blk;
-}
-
-CacheBlk*
-LRU::findVictim(Addr addr)
-{
- int set = extractSet(addr);
- // grab a replacement candidate
- BlkType *blk = nullptr;
- for (int i = assoc - 1; i >= 0; i--) {
- BlkType *b = sets[set].blks[i];
- if (b->way < allocAssoc) {
- blk = b;
- break;
- }
- }
- assert(!blk || blk->way < allocAssoc);
-
- if (blk && blk->isValid()) {
- DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
- set, regenerateBlkAddr(blk->tag, set));
- }
-
- return blk;
-}
-
-void
-LRU::insertBlock(PacketPtr pkt, BlkType *blk)
-{
- BaseSetAssoc::insertBlock(pkt, blk);
-
- int set = extractSet(pkt->getAddr());
- sets[set].moveToHead(blk);
-}
-
-void
-LRU::invalidate(CacheBlk *blk)
-{
- BaseSetAssoc::invalidate(blk);
-
- // should be evicted before valid blocks
- int set = blk->set;
- sets[set].moveToTail(blk);
-}
-
-LRU*
-LRUParams::create()
-{
- return new LRU(this);
-}
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
deleted file mode 100644
index d38b94e..0000000
--- a/src/mem/cache/tags/lru.hh
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2012-2013 ARM Limited
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * Declaration of a LRU tag store.
- * The LRU tags guarantee that the true least-recently-used way in
- * a set will always be evicted.
- */
-
-#ifndef __MEM_CACHE_TAGS_LRU_HH__
-#define __MEM_CACHE_TAGS_LRU_HH__
-
-#include "mem/cache/tags/base_set_assoc.hh"
-#include "params/LRU.hh"
-
-class LRU : public BaseSetAssoc
-{
- public:
- /** Convenience typedef. */
- typedef LRUParams Params;
-
- /**
- * Construct and initialize this tag store.
- */
- LRU(const Params *p);
-
- /**
- * Destructor
- */
- ~LRU() {}
-
- CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
- CacheBlk* findVictim(Addr addr);
- void insertBlock(PacketPtr pkt, BlkType *blk);
- void invalidate(CacheBlk *blk);
-};
-
-#endif // __MEM_CACHE_TAGS_LRU_HH__
diff --git a/src/mem/cache/tags/random_repl.cc
b/src/mem/cache/tags/random_repl.cc
deleted file mode 100644
index ab51f64..0000000
--- a/src/mem/cache/tags/random_repl.cc
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2014 The Regents of The University of Michigan
- * Copyright (c) 2016 ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
- */
-
-/**
- * @file
- * Definitions of a random replacement tag store.
- */
-
-#include "mem/cache/tags/random_repl.hh"
-
-#include "base/random.hh"
-#include "debug/CacheRepl.hh"
-#include "mem/cache/base.hh"
-
-RandomRepl::RandomRepl(const Params *p)
- : BaseSetAssoc(p)
-
-{
-}
-
-CacheBlk*
-RandomRepl::accessBlock(Addr addr, bool is_secure, Cycles &lat)
-{
- return BaseSetAssoc::accessBlock(addr, is_secure, lat);
-}
-
-CacheBlk*
-RandomRepl::findVictim(Addr addr)
-{
- CacheBlk *blk = BaseSetAssoc::findVictim(addr);
- unsigned set = extractSet(addr);
-
- // if all blocks are valid, pick a replacement at random
- if (blk && blk->isValid()) {
- // find a random index within the bounds of the set
- int idx = random_mt.random<int>(0, assoc - 1);
- blk = sets[set].blks[idx];
- // Enforce allocation limit
- while (blk->way >= allocAssoc) {
- idx = (idx + 1) % assoc;
- blk = sets[set].blks[idx];
- }
-
- assert(idx < assoc);
- assert(idx >= 0);
- assert(blk->way < allocAssoc);
-
- DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
- blk->set, regenerateBlkAddr(blk->tag, blk->set));
- }
-
- return blk;
-}
-
-void
-RandomRepl::insertBlock(PacketPtr pkt, BlkType *blk)
-{
- BaseSetAssoc::insertBlock(pkt, blk);
-}
-
-void
-RandomRepl::invalidate(CacheBlk *blk)
-{
- BaseSetAssoc::invalidate(blk);
-}
-
-RandomRepl*
-RandomReplParams::create()
-{
- return new RandomRepl(this);
-}
diff --git a/src/mem/cache/tags/random_repl.hh
b/src/mem/cache/tags/random_repl.hh
deleted file mode 100644
index 8f08a70..0000000
--- a/src/mem/cache/tags/random_repl.hh
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2014 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
- */
-
-/**
- * @file
- * Declaration of a random replacement tag store.
- * The RandomRepl tags first try to evict an invalid
- * block. If no invalid blocks are found, a candidate
- * for eviction is found at random.
- */
-
-#ifndef __MEM_CACHE_TAGS_RANDOM_REPL_HH__
-#define __MEM_CACHE_TAGS_RANDOM_REPL_HH__
-
-#include "mem/cache/tags/base_set_assoc.hh"
-#include "params/RandomRepl.hh"
-
-class RandomRepl : public BaseSetAssoc
-{
- public:
- /** Convenience typedef. */
- typedef RandomReplParams Params;
-
- /**
- * Construct and initiliaze this tag store.
- */
- RandomRepl(const Params *p);
-
- /**
- * Destructor
- */
- ~RandomRepl() {}
-
- CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
- CacheBlk* findVictim(Addr addr);
- void insertBlock(PacketPtr pkt, BlkType *blk);
- void invalidate(CacheBlk *blk);
-};
-
-#endif // __MEM_CACHE_TAGS_RANDOM_REPL_HH__
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index ad65ef7..50885fb 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -858,6 +858,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -901,7 +902,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -916,6 +917,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1697,6 +1708,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1740,7 +1752,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1755,6 +1767,16 @@
size=1048576
tag_latency=12
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 1c09997..b16d8c9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -769,6 +769,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -812,7 +813,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -827,6 +828,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1519,6 +1530,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1562,7 +1574,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1577,6 +1589,16 @@
size=1048576
tag_latency=12
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index bcf1aa1..8cbea51 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -837,6 +837,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -879,7 +880,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -893,6 +894,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1653,6 +1664,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1695,7 +1707,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1709,6 +1721,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index d65c440..8a12ce2 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -740,6 +740,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -782,7 +783,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -796,6 +797,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -1459,6 +1470,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -1501,7 +1513,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -1515,6 +1527,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 4ef1d1b..67662fb 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -403,6 +403,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -445,7 +446,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -459,6 +460,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -785,6 +796,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -827,7 +839,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -841,6 +853,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 9e59e49..5ec3d6c 100644
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -399,6 +399,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -441,7 +442,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -455,6 +456,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -777,6 +788,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -819,7 +831,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -833,6 +845,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index e061f70..b9dffa5 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index e92ae69..0d17d21 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 2c21341..b7b65f9 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 721f1a5..de83a55 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 609dcfe..01d142c 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 5da6802..0a21511 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 87b4a60..6d789f0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 01bc995..6a950c6 100644
---
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -403,6 +403,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -445,7 +446,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -459,6 +460,16 @@
sequential_access=false
size=1048576
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -785,6 +796,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -827,7 +839,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -841,6 +853,16 @@
sequential_access=false
size=1048576
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 4448abd..14f6ddd 100644
---
a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++
b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -400,6 +400,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
+repl_policy=system.cpu0.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -443,7 +444,7 @@
use_master_id=true
[system.cpu0.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -458,6 +459,16 @@
size=1048576
tag_latency=12
+[system.cpu0.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
@@ -781,6 +792,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
+repl_policy=system.cpu1.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -824,7 +836,7 @@
use_master_id=true
[system.cpu1.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -839,6 +851,17 @@
size=1048576
tag_latency=12
+
+[system.cpu1.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 72771fa..43a1cc4 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -712,6 +712,7 @@
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
+repl_policy=system.cpu.l2cache.repl_policy
response_latency=12
sequential_access=false
size=1048576
@@ -755,7 +756,7 @@
use_master_id=true
[system.cpu.l2cache.tags]
-type=RandomRepl
+type=BaseSetAssoc
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
@@ -770,6 +771,16 @@
size=1048576
tag_latency=12
+[system.cpu.l2cache.repl_policy]
+type=RandomRP
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
--
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Gerrit-Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
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Gerrit-Owner: Daniel Carvalho <***@yahoo.com.br>