[PATCH v5 0/7] spi: add support for octal mode

[Yogesh Narayan Gaur]

Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).

Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem framework and m25p80.c device file.
* Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode.
Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash.
* Add mode bit required for octal mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].

Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.

***@lxxx:~# cat /proc/mtd
dev: size erasesize name
mtd0: 04000000 00001000 "spi0.0"
mtd1: 04000000 00001000 "spi0.1"
***@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
Copied 16777216 bytes from address 0x00000000 in flash to 0read

real 0m2.792s
user 0m0.000s
sys 0m2.790s
***@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
Copied 16777216 bytes from address 0x00000000 in flash to 0read

real 0m0.441s
user 0m0.000s
sys 0m0.440s
***@ls1012ardb:~#

Flash device MTD0 configured in 1-1-1 protocol.
Flash device MTD1 configured in 1-1-8 protocol.

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384&state=*
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402

Yogesh Gaur (7):
spi: add support for octal mode I/O data transfer
spi: spi-mem: add support for octal mode I/O data transfer
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba
mtd: m25p80: add support of octal mode I/O transfer
spi: nxp-fspi: add octal mode flag bit for octal support
arm64: dts: lx2160a: update fspi node

Changes for v5:
- Modified string 'octo' as 'octal' in all patches.
Changes for v4:
- Rebase on top of v4.20-rc2.
- Modify octo entries enum value in spi.h.
Changes for v3:
- Add octo mode support in spi_setup().
- Rename all patches with 'octal' string modified as 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh.

drivers/mtd/devices/m25p80.c | 9 ++++++++-
drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
drivers/spi/spi-mem.c | 9 ++++++++-
drivers/spi/spi-nxp-fspi.c | 4 ++--
drivers/spi/spi.c | 12 ++++++++++--
include/linux/mtd/spi-nor.h | 8 ++++++++
include/linux/spi/spi.h | 4 +++-
8 files changed, 59 insertions(+), 10 deletions(-)

[Yogesh Narayan Gaur]

Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires

Signed-off-by: Yogesh Gaur <***@nxp.com>
Reviewed-by: Boris Brezillon <***@bootlin.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- Rebase on top of v4.20-rc2
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.
---
drivers/spi/spi.c | 12 ++++++++++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca5940..95249b8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-tx-bus-width %d not supported\n",
@@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-rx-bus-width %d not supported\n",
@@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(&spi->dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa..0c1ca5d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
-#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
+#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
int irq;
void *controller_state;
void *controller_data;

[Yogesh Narayan Gaur]

Add support for octal mode I/O data transfer in spi-mem framework.

Signed-off-by: Yogesh Gaur <***@nxp.com>
Reviewed-by: Boris Brezillon <***@bootlin.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2 version.

drivers/spi/spi-mem.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 62a7b80..5e15d62 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -12,7 +12,7 @@

#include "internals.h"

-#define SPI_MEM_MAX_BUSWIDTH 4
+#define SPI_MEM_MAX_BUSWIDTH 8

/**
* spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
@@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)

break;

+ case 8:
+ if ((tx && (mode & SPI_TX_OCTAL)) ||
+ (!tx && (mode & SPI_RX_OCTAL)))
+ return 0;
+
+ break;
+
default:
break;
}

[Yogesh Narayan Gaur]

Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.

Signed-off-by: Yogesh Gaur <***@nxp.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.

drivers/mtd/devices/m25p80.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;

- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;

if (spi->mode & SPI_TX_QUAD)

[Yogesh Narayan Gaur]

Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.

Signed-off-by: Yogesh Gaur <***@nxp.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- None

drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index a35013b..b65f27c 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
if (!ctlr)
return -ENOMEM;

- ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
+ SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;

f = spi_controller_get_devdata(ctlr);
f->dev = dev;

[Yogesh Narayan Gaur]

Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.

Signed-off-by: Yogesh Gaur <***@nxp.com>
---
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None

arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};

mt35xu512aba1: ***@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};

[Yogesh Narayan Gaur]

Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.

Signed-off-by: Vignesh R <***@ti.com>
Signed-off-by: Yogesh Gaur <***@nxp.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh

drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7a2176d..41ba90b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},

/* PMC */

[Yogesh Narayan Gaur]

- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command

- Entry of macros in _convert_3to4_xxx function

- Add flag specifying flash support octal read commands.

Signed-off-by: Vignesh R <***@ti.com>
Signed-off-by: Yogesh Gaur <***@nxp.com>
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh

drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++++++++--
include/linux/mtd/spi-nor.h | 8 ++++++++
2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 398d273..7a2176d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */

int (*quad_enable)(struct spi_nor *nor);
};
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },

{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};

return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -2093,7 +2098,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,

- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -2110,7 +2115,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,

- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}

+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@@ -73,9 +77,13 @@
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */

[Yogesh Narayan Gaur]

Hi,

-----Original Message-----
Sent: Monday, December 10, 2018 4:57 PM
Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write
commands
On Mon, 10 Dec 2018 11:17:20 +0000

Post by Vignesh R
Hi Boris,

-----Original Message-----
Sent: Monday, December 10, 2018 4:27 PM
Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal
Read/Write commands
On Mon, 3 Dec 2018 08:39:18 +0000

Post by Yogesh Narayan Gaur
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.

Looks like the SoB and Author lines do not match
Can you find a way to make them match?

I am sending the patches with my smtp server of OutlookOffice and in that my

user name is "Yogesh Narayan Gaur" and in gitconfig of my Linux machine I set
user name as "Yogesh Gaur".

Post by Vignesh R
Is it mandatory to have same Author name in SoB and Author lines, if yes I

would change the settings in gitconfig file.
We have scripts that check that the author/committer has its SoB, depending on
how strict the check is, it might complaint that SoB an author/committer do not
match, so yes, please change gitconfig to make them match.

Ok, sure. In all other future patches would modify my Author name.

Thanks,
Boris

[T***@microchip.com]

Hi, Yogesh,

Post by Yogesh Narayan Gaur
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
---
- Modified string 'octo' with 'octal'.
- None
- Modified string 'octal' with 'octo'.
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++++++++--
include/linux/mtd/spi-nor.h | 8 ++++++++
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 398d273..7a2176d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
int (*quad_enable)(struct spi_nor *nor);
};
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -2093,7 +2098,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -2110,7 +2115,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+> /* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],

At the end of spi_nor_init_params we check the conditions for parsing the sfdp.
Shouldn't SPI_NOR_OCTAL_READ trigger the sfdp parsing when SPI_NOR_SKIP_SFDP is
not set?

Post by Yogesh Narayan Gaur
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@

Can you please s/octo/octal on these as well:
$ grep -ni octo include/linux/mtd/spi-nor.h
471: * As a matter of performances, it is relevant to use Octo SPI protocols first,
492:#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
501: * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
515:#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)

thanks,
ta

[Boris Brezillon]

Hi Mark,

On Mon, 3 Dec 2018 08:39:00 +0000

Post by Yogesh Narayan Gaur
spi: add support for octal mode I/O data transfer
spi: spi-mem: add support for octal mode I/O data transfer

Can you take those 2 patches in your tree for 4.21/5.0?

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba
mtd: m25p80: add support of octal mode I/O transfer
spi: nxp-fspi: add octal mode flag bit for octal support

I'll queue these ones after 4.21-rc1/5.0-rc1 is out (which means
they'll appear in 4.22/5.1).

Post by Yogesh Narayan Gaur
arm64: dts: lx2160a: update fspi node

[Vignesh R]

Hi Boris,

Post by Boris Brezillon
Hi Mark,
On Mon, 3 Dec 2018 08:39:00 +0000

Post by Yogesh Narayan Gaur
spi: add support for octal mode I/O data transfer
spi: spi-mem: add support for octal mode I/O data transfer

Can you take those 2 patches in your tree for 4.21/5.0?

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba

Could you consider merging these two patches alone for v4.21?
These can be applied independent of other patches in the series and
would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver.

Post by Boris Brezillon

Post by Yogesh Narayan Gaur
mtd: m25p80: add support of octal mode I/O transfer
spi: nxp-fspi: add octal mode flag bit for octal support

I'll queue these ones after 4.21-rc1/5.0-rc1 is out (which means
they'll appear in 4.22/5.1).

Post by Yogesh Narayan Gaur
arm64: dts: lx2160a: update fspi node

[Boris Brezillon]

On Wed, 5 Dec 2018 17:25:12 +0530

Post by Vignesh R

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba

Could you consider merging these two patches alone for v4.21?
These can be applied independent of other patches in the series and
would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver.

Yep, I'll queue them to spi-nor/next.

Post by Vignesh R

Post by Yogesh Narayan Gaur
spi: nxp-fspi: add octal mode flag bit for octal support

Mark, I think you can pick this one too.

[Mark Brown]

Post by Boris Brezillon

Post by Yogesh Narayan Gaur
spi: nxp-fspi: add octal mode flag bit for octal support

Mark, I think you can pick this one too.

I don't have this any more, it looked like this was stuck behind the
otehr MTD changes which seemed to have problems. If someone could
resend?

[Yogesh Narayan Gaur]

Hi Boris,

-----Original Message-----
Sent: Wednesday, December 5, 2018 6:16 PM
Subject: Re: [PATCH v5 0/7] spi: add support for octal mode
On Wed, 5 Dec 2018 17:25:12 +0530

Post by Vignesh R

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba

Could you consider merging these two patches alone for v4.21?
These can be applied independent of other patches in the series and
would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver.

Yep, I'll queue them to spi-nor/next.

Post by Vignesh R

Post by Yogesh Narayan Gaur
spi: nxp-fspi: add octal mode flag bit for octal support

Mark, I think you can pick this one too.

This patch is dependent on the series [1] which is yet to be applied by you, please apply.

--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402

[Boris Brezillon]

On Thu, 6 Dec 2018 04:20:26 +0000

Post by Vignesh R
Hi Boris,

-----Original Message-----
Sent: Wednesday, December 5, 2018 6:16 PM
Subject: Re: [PATCH v5 0/7] spi: add support for octal mode
On Wed, 5 Dec 2018 17:25:12 +0530

Post by Vignesh R

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba

Could you consider merging these two patches alone for v4.21?
These can be applied independent of other patches in the series and
would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver.

Yep, I'll queue them to spi-nor/next.

Post by Vignesh R

Post by Yogesh Narayan Gaur
spi: nxp-fspi: add octal mode flag bit for octal support

Mark, I think you can pick this one too.

This patch is dependent on the series [1] which is yet to be applied by you, please apply.

By me? I can't apply SPI patches.

[Yogesh Narayan Gaur]

Hi Boris,

-----Original Message-----
Sent: Thursday, December 6, 2018 12:16 PM
Subject: Re: [PATCH v5 0/7] spi: add support for octal mode
On Thu, 6 Dec 2018 04:20:26 +0000

Post by Vignesh R
Hi Boris,

-----Original Message-----
Sent: Wednesday, December 5, 2018 6:16 PM
Subject: Re: [PATCH v5 0/7] spi: add support for octal mode
On Wed, 5 Dec 2018 17:25:12 +0530

Post by Vignesh R

Post by Yogesh Narayan Gaur
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba

Could you consider merging these two patches alone for v4.21?
These can be applied independent of other patches in the series
and would allow supporting OSPI flash at SPI NOR level with Cadence QSPI

driver.

Post by Vignesh R

Yep, I'll queue them to spi-nor/next.

Post by Vignesh R

Post by Yogesh Narayan Gaur
spi: nxp-fspi: add octal mode flag bit for octal support

Mark, I think you can pick this one too.

This patch is dependent on the series [1] which is yet to be applied by you,

please apply.
By me? I can't apply SPI patches.

Sorry for ignorance. Did patches needs to be applied by Mark Brown, should I resend the patch series again?
Also can you please review the series [1] and add your Reviewed-by tag.

--
Regards
Yogesh Gaur

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402

[Mark Brown]

Post by Yogesh Narayan Gaur
Sorry for ignorance. Did patches needs to be applied by Mark Brown, should I resend the patch series again?
Also can you please review the series [1] and add your Reviewed-by tag.

As I said in my reply earlier today in the same thread:

| I don't have this any more, it looked like this was stuck behind the
| otehr MTD changes which seemed to have problems. If someone could
| resend?

so please resend.

[Mark Brown]

Post by Boris Brezillon
Hi Mark,

Please don't top post, reply in line with needed context. This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion is being addressed.

Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes your messages much
easier to read and reply to.

Post by Boris Brezillon
Patch has been resend [1], this patch is depends on the series of patch[2] and this series has been applied by Boris already.
[1] https://patchwork.ozlabs.org/patch/1010253/

This appears to be an MTD patch? The subject is "mtd: m25p80: add
support of octal mode I/O transfer". MTD patches normally go via the
MTD tree which is maintained by a group of people including Boris but
not me.

Please include human readable descriptions of things like commits and
issues being discussed in e-mail in your mails, this makes them much
easier for humans to read especially when they have no internet access.
I do frequently catch up on my mail on flights or while otherwise
travelling so this is even more pressing for me than just being about
making things a bit easier to read.

[Boris Brezillon]

On Mon, 10 Dec 2018 08:39:20 +0000

Post by Vignesh R
Hi Boris,
Sorry for confusion.
My intention was just to point to the correct patch number only. Earlier you have asked Mark to pick the patch [1] but that patch number was not correct.

Look at the context in [1] (we have good reasons to reply inline instead
of top-posting). I asked Mark to pick "spi: nxp-fspi: add octal mode
flag bit for octal support", not the m25p80 changes. I was wrong
though, as the patch I pointed to depends on your nxp-fspi patchset
which as not been merged yet.

Post by Vignesh R
[1] https://lkml.org/lkml/2018/12/5/758

[Mark Brown]

The patch

spi: add support for octal mode I/O data transfer

has been applied to the spi tree at

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 6b03061f882de49b83ccf44beb3a12c920a2da1b Mon Sep 17 00:00:00 2001
From: Yogesh Narayan Gaur <***@nxp.com>
Date: Mon, 3 Dec 2018 08:39:06 +0000
Subject: [PATCH] spi: add support for octal mode I/O data transfer

Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires

Signed-off-by: Yogesh Gaur <***@nxp.com>
Reviewed-by: Boris Brezillon <***@bootlin.com>
Signed-off-by: Mark Brown <***@kernel.org>
---
drivers/spi/spi.c | 12 ++++++++++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b6fd8ea8ac0d..18ebc400249c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1633,6 +1633,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-tx-bus-width %d not supported\n",
@@ -1651,6 +1654,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-rx-bus-width %d not supported\n",
@@ -2839,7 +2845,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2848,7 +2855,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(&spi->dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa5ab90..0c1ca5dedbb4 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
-#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
+#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
int irq;
void *controller_state;
void *controller_data;