[Mesa-dev] [PATCH 00/30] i965: Add support for I915_FORMAT_MOD_Y_TILED_CCS

[Jason Ekstrand]

This series is a rework of Ben's series to enable the CCS format modifier.
It started as an attempt to rebase his original patches on top of my
resolve reworks inside the miptree code. However, as I started to dive
deeper, I found a number of subtle issues:

1) Thanks to the terrible set of INTEL_AUX_DISABLE_* flags that we use to
choose what aux buffers to use, we were set up to never use CCS_E for
any external buffers. Even when Y-tiled on gen9, the most they would
ever get was CCS_D.

2) Whether to do a full or partial resolve or not was based on is_scanout
and not on the actual modifier. If we use I915_FORMAT_MOD_Y_TILED (not
the CCS modifier) and choose to use CCS_E with it, it would only get
partial resolves and not full resolves. Of course, this wasn't
actually a problem thanks to problem 1 above.

3) If a user ever imported an image with I915_FORMAT_MOD_Y_TILED_CCS
through EGL or GBM and did glClear on it, they would get a fast clear
with no way to force a resolve before handing it off to the other
process. Since the other process doesn't know the clear color, this
means that any blocks in the clear state in the surface will get
whatever random clear color process B thinks it has.

4) There were three different places where we computed the pitch of the
CCS and they all did so differently. When we go to create the image,
we would allocate the CCS with the same pitch as the main surface. We
would then calculate the CCS pitch with ISL when we created mt->mcs_buf.
Finally, we had a different mechanism to compute the pitch when we pass
it back to the user. Fortunately, the first only caused us to over-
allocate and I think the last two were equivalent (at least for the
simple case) so nothing exploded.

5) Thanks again to our confusing aux enable/disable, we haven't been doing
multisample fast-clears since cec30a666930ddb8476a9452a89364a24979ff62
around a year ago.

This series takes a bit more round-about approach to enabling the CCS
modifier that should fix these issues:

* Patches 1-5 do a bit of refactoring and then rework the way we choose
the type of aux compression to use. They move us away from the crazy
enable/disable system to a simple choice system. This fixes (1) and (5)
above.

* Patches 6-15 refactor things so that we have only one path for going
from a __DRIimage to an intel_mipmap_tree. This was rather painful
because we have to be careful to take into account the differences
between window system images regular images.

* Patches 16-22 rework image creation and import to use ISL to do their
surface layout calculations. Previously, all of the surface layout
calculations were simply hand-rolled here. In the particular case of
images, the hand-rolling was fairly safe because they were only ever
simple 2D non-array images. However, with the addition of CCS, things
were going to get a bit tricky.

* Patches 23-30 add support for I915_FORMAT_MOD_Y_TILED.

I've tested this series on our Jenkins system which runs piglit as well as
the OpenGL and OpenGL ES test suites. Both piglit and the OpenGL ES suite
have some number of EGL tests which I hope have tested some of this. I've
also tested with kmscube and have verified that I get basically the same
bandwidth numbers as Ben got on his original series, so I think CCS is
working properly.

This series can be found here:

https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-ccs-mod

Cc: Ben Widawsky <***@bwidawsk.net>
Cc: Daniel Stone <***@collabora.com>
Cc: Varad Gautam <***@collabora.com>
Cc: Chad Versace <***@chromium.org>
Cc: Topi Pohjolainen <***@intel.com>

Ben Widawsky (6):
i965/miptree: Add a return for updating of winsys
i965/miptree: Allocate mt earlier in update winsys
i965: Support images with aux buffers
i965/miptree: Allocate mcs_buf for an image's CCS
i965: Pretend that CCS modified images are two planes
i965: Advertise the CCS modifier

Jason Ekstrand (24):
i965/miptree: Delete the layered rendering resolve
i965/miptree: Rename the non_msrt_mcs functions to _ccs
i965: Don't bother with HiZ in renderbuffer_move_to_temp
i965: Clamp clear colors to the representable range
i965/miptree: Rework aux enabling
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
i965/miptree: Add tile_x/y to total_width/height
i965/miptree: Set level_x/h in create_for_dri_image
i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
i965/miptree: Add an explicit format parameter to create_for_dri_image
i965/miptree: Add support for window system images to
create_for_dri_image
i965: Use create_for_dri_image in intel_update_image_buffer
i965/miptree: Move CCS allocation into create_for_dri_image
i965: Add an isl_device to intel_screen
intel/isl: Add basic modifier introspection
intel/isl: Add a helper to convert tilings fro ISL to i915
i965/screen: Use ISL for allocating image BOs
i965/screen: Use ISL for doing image import checks
i965/screen: Drop get_tiled_height
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
i965/screen: Support import and export of surfaces with CCS
i965/miptree: More conservatively resolve external images

src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.c | 4 +-
src/intel/isl/isl.h | 28 +-
src/intel/isl/isl_drm.c | 93 +++++
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 44 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++
src/mesa/drivers/dri/i965/intel_fbo.c | 30 +-
src/mesa/drivers/dri/i965/intel_image.h | 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 496 ++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 77 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 216 +++++++----
src/mesa/drivers/dri/i965/intel_screen.h | 4 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 98 +----
16 files changed, 767 insertions(+), 377 deletions(-)
create mode 100644 src/intel/isl/isl_drm.c

[Jason Ekstrand]

This function is only used on gen4-5 which don't support HiZ.
---
src/mesa/drivers/dri/i965/intel_fbo.c | 4 ----
1 file changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 864ff32..ee4aba9 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -960,10 +960,6 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
irb->mt->num_samples,
layout_flags);

- if (intel_miptree_wants_hiz_buffer(brw, new_mt)) {
- intel_miptree_alloc_hiz(brw, new_mt);
- }
-
intel_miptree_copy_teximage(brw, intel_image, new_mt, invalidate);

intel_miptree_reference(&irb->mt, intel_image->mt);

[Chad Versace]

Post by Jason Ekstrand
This function is only used on gen4-5 which don't support HiZ.

Yup. Did I write that code?

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +++++++++++++--------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
3 files changed, 25 insertions(+), 40 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index e8993a8..00092ee 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to recover
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3dddfae..0f6d542 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -101,9 +101,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
}
}

-bool
-intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
- unsigned tiling)
+static bool
+intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling)
{
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
@@ -141,9 +140,9 @@ intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
* - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
* non-MSRTs only.
*/
-bool
-intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+static bool
+intel_miptree_supports_ccs(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
if (brw->gen < 7)
@@ -243,9 +242,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
return mt->num_samples <= 1;
}

-bool
-intel_miptree_supports_lossless_compressed(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+static bool
+intel_miptree_supports_ccs_e(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
/* For now compression is only enabled for integer formats even though
* there exist supported floating point formats also. This is a heuristic
@@ -257,8 +256,7 @@ intel_miptree_supports_lossless_compressed(struct brw_context *brw,
if (_mesa_get_format_datatype(mt->format) == GL_FLOAT)
return false;

- /* Fast clear mechanism and lossless compression go hand in hand. */
- if (!intel_miptree_supports_non_msrt_fast_clear(brw, mt))
+ if (!intel_miptree_supports_ccs(brw, mt))
return false;

/* Fast clear can be also used to clear srgb surfaces by using equivalent
@@ -512,7 +510,7 @@ intel_miptree_create_layout(struct brw_context *brw,
* 7 | ? | ?
* 6 | ? | ?
*/
- if (intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_miptree_supports_ccs(brw, mt)) {
if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
@@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
* clear actually occurs or when compressed single sampled buffer is
* written by the GPU for the first time.
*/
- if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);

@@ -747,10 +745,10 @@ intel_miptree_create(struct brw_context *brw,
const bool is_lossless_compressed =
unlikely(!lossless_compression_disabled) &&
brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_lossless_compressed(brw, mt);
+ intel_miptree_supports_ccs_e(brw, mt);

if (is_lossless_compressed) {
- intel_miptree_alloc_non_msrt_mcs(brw, mt, is_lossless_compressed);
+ intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
}
}

@@ -856,8 +854,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
- if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) {
+ if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
+ intel_miptree_supports_ccs(intel, singlesample_mt)) {
singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
}

@@ -1552,9 +1550,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
}

bool
-intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_lossless_compressed)
+intel_miptree_alloc_ccs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ bool is_ccs_e)
{
assert(mt->mcs_buf == NULL);
assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
@@ -1592,8 +1590,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags =
- is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;

buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1610,7 +1607,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_lossless_compressed) {
+ if (is_ccs_e) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f7b8e67..aa33967 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -654,21 +654,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
const struct intel_mipmap_tree *mt);

bool
-intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
- unsigned tiling);
-
-bool
-intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
- const struct intel_mipmap_tree *mt);
-
-bool
-intel_miptree_supports_lossless_compressed(struct brw_context *brw,
- const struct intel_mipmap_tree *mt);
-
-bool
-intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_lossless_compressed);
+intel_miptree_alloc_ccs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ bool is_ccs_e);

enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,

[Chad Versace]

Post by Jason Ekstrand
While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +++++++++++++--------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
3 files changed, 25 insertions(+), 40 deletions(-)

This patch greatly clarifies the code, making it more precise. I'm
always in favor for replacing fuzzy, english phrases in code with
terse, precise terms.

Post by Jason Ekstrand
@@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
* clear actually occurs or when compressed single sampled buffer is
* written by the GPU for the first time.
*/
- if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {

That was my favorite hunk of the patch. Now it's obvious the the two
lines are checking essentially the same thing. In fact, we can probably
drop the tiling check here. The miptree check should be sufficient (and
if it's not, that's a bug in my opinion).

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

Post by Jason Ekstrand

Post by Jason Ekstrand
While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45

+++++++++++++--------------

Post by Jason Ekstrand
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
3 files changed, 25 insertions(+), 40 deletions(-)

This patch greatly clarifies the code, making it more precise. I'm
always in favor for replacing fuzzy, english phrases in code with
terse, precise terms.

Post by Jason Ekstrand
@@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
* clear actually occurs or when compressed single sampled buffer is
* written by the GPU for the first time.
*/
- if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {

That was my favorite hunk of the patch. Now it's obvious the the two
lines are checking essentially the same thing. In fact, we can probably
drop the tiling check here. The miptree check should be sufficient (and
if it's not, that's a bug in my opinion).

If only... Unfortunately, we need intel_miptree_supports_ccs to *not* know
about tiling because we have to decide whether or not to do CCS so that we
can deside if we need HALIGN16 so that we can layout the miptree so that we
can decide tiling. Yes, it's terrible.

[Chad Versace]

Post by Jason Ekstrand

Post by Jason Ekstrand
While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.
---
  src/mesa/drivers/dri/i965/brw_blorp.c         |  2 +-
  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45

+++++++++++++--------------

Post by Jason Ekstrand
  src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
  3 files changed, 25 insertions(+), 40 deletions(-)

This patch greatly clarifies the code, making it more precise. I'm
always in favor for replacing fuzzy, english phrases in code with
terse, precise terms.

Post by Jason Ekstrand
@@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
      * clear actually occurs or when compressed single sampled buffer is
      * written by the GPU for the first time.
      */
-   if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
-       intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+   if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+       intel_miptree_supports_ccs(brw, mt)) {

That was my favorite hunk of the patch. Now it's obvious the the two
lines are checking essentially the same thing. In fact, we can probably
drop the tiling check here. The miptree check should be sufficient (and
if it's not, that's a bug in my opinion).
If only...  Unfortunately, we need intel_miptree_supports_ccs to *not* know
about tiling because we have to decide whether or not to do CCS so that we can
deside if we need HALIGN16 so that we can layout the miptree so that we can
decide tiling.  Yes, it's terrible.

i965 calls intel_miptree_supports_ccs() on the miptree before its
construction is complete? I didn't see that until now. Ugh.

[Pohjolainen, Topi]

Post by Jason Ekstrand
While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +++++++++++++--------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
3 files changed, 25 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index e8993a8..00092ee 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to recover
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3dddfae..0f6d542 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -101,9 +101,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
}
}
-bool
-intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
- unsigned tiling)
+static bool
+intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling)
{
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
@@ -141,9 +140,9 @@ intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
* - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
* non-MSRTs only.
*/
-bool
-intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+static bool
+intel_miptree_supports_ccs(struct brw_context *brw,

Could be const as well.

Post by Jason Ekstrand
+ const struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
if (brw->gen < 7)
@@ -243,9 +242,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
return mt->num_samples <= 1;
}
-bool
-intel_miptree_supports_lossless_compressed(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+static bool
+intel_miptree_supports_ccs_e(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
/* For now compression is only enabled for integer formats even though
* there exist supported floating point formats also. This is a heuristic
@@ -257,8 +256,7 @@ intel_miptree_supports_lossless_compressed(struct brw_context *brw,
if (_mesa_get_format_datatype(mt->format) == GL_FLOAT)
return false;
- /* Fast clear mechanism and lossless compression go hand in hand. */
- if (!intel_miptree_supports_non_msrt_fast_clear(brw, mt))
+ if (!intel_miptree_supports_ccs(brw, mt))
return false;
/* Fast clear can be also used to clear srgb surfaces by using equivalent
@@ -512,7 +510,7 @@ intel_miptree_create_layout(struct brw_context *brw,
* 7 | ? | ?
* 6 | ? | ?
*/
- if (intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_miptree_supports_ccs(brw, mt)) {
if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
@@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
* clear actually occurs or when compressed single sampled buffer is
* written by the GPU for the first time.
*/
- if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
+ if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
@@ -747,10 +745,10 @@ intel_miptree_create(struct brw_context *brw,
const bool is_lossless_compressed =
unlikely(!lossless_compression_disabled) &&
brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_lossless_compressed(brw, mt);
+ intel_miptree_supports_ccs_e(brw, mt);
if (is_lossless_compressed) {
- intel_miptree_alloc_non_msrt_mcs(brw, mt, is_lossless_compressed);
+ intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
}
}
@@ -856,8 +854,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
- if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) {
+ if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
+ intel_miptree_supports_ccs(intel, singlesample_mt)) {
singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
}
@@ -1552,9 +1550,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
}
bool
-intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_lossless_compressed)
+intel_miptree_alloc_ccs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ bool is_ccs_e)
{
assert(mt->mcs_buf == NULL);
assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
@@ -1592,8 +1590,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags =
- is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1610,7 +1607,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_lossless_compressed) {
+ if (is_ccs_e) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f7b8e67..aa33967 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -654,21 +654,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
const struct intel_mipmap_tree *mt);
bool
-intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
- unsigned tiling);
-
-bool
-intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
- const struct intel_mipmap_tree *mt);
-
-bool
-intel_miptree_supports_lossless_compressed(struct brw_context *brw,
- const struct intel_mipmap_tree *mt);
-
-bool
-intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_lossless_compressed);
+intel_miptree_alloc_ccs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ bool is_ccs_e);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

We never fast-clear more than the base slice (LOD 0, layer 0) anyway, so
layered rendering without a resolve is always perfectly safe. Should
this ever change in the future, we'll have to put some sort of resolve
back in but we can cross that bridge when we come to it.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 --------------
1 file changed, 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 02e74ca..3dddfae 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2590,20 +2590,6 @@ intel_miptree_prepare_render(struct brw_context *brw,
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
false, false);
}
-
- /* For layered rendering non-compressed fast cleared buffers need to be
- * resolved. Surface state can carry only one fast color clear value
- * while each layer may have its own fast clear color value. For
- * compressed buffers color value is available in the color buffer.
- */
- if (layer_count > 1 &&
- !(mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
- !intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 8);
-
- intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
- false, false);
- }
}

void

[Chad Versace]

Post by Jason Ekstrand
We never fast-clear more than the base slice (LOD 0, layer 0) anyway, so
layered rendering without a resolve is always perfectly safe. Should
this ever change in the future, we'll have to put some sort of resolve
back in but we can cross that bridge when we come to it.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 --------------
1 file changed, 14 deletions(-)

Yep, do_single_blorp_clear() bails on layered renderbuffers.

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 023c6aa..3bc6827 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -915,7 +915,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
*/
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, image->format,
- 0, image->width, image->height, 1,
+ image->offset, image->width, image->height, 1,
image->pitch,
MIPTREE_LAYOUT_DISABLE_AUX);
if (mt == NULL)
@@ -942,8 +942,6 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}

- mt->offset = image->offset;
-
return mt;
}

[Pohjolainen, Topi]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 023c6aa..3bc6827 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -915,7 +915,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
*/
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, image->format,
- 0, image->width, image->height, 1,
+ image->offset, image->width, image->height, 1,
image->pitch,
MIPTREE_LAYOUT_DISABLE_AUX);
if (mt == NULL)
@@ -942,8 +942,6 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}
- mt->offset = image->offset;
-
return mt;
}
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

Starting with Sky Lake, we can clear to arbitrary floats or integers.
Unfortunately, the hardware isn't particularly smart when it comes
sampling from that clear color. If the clear color is out of range for
the surface format, it will happily return whatever we put in the
surface state packet unmodified. In order to avoid returning bogus
values for surfaces with a limited range, we need to do some clamping.

Cc: "17.1" <mesa-***@lists.freedesktop.org>
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 2416079..3751785 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -364,6 +364,46 @@ brw_meta_convert_fast_clear_color(const struct brw_context *brw,
break;
}

+ switch (_mesa_get_format_datatype(mt->format)) {
+ case GL_UNSIGNED_NORMALIZED:
+ for (int i = 0; i < 4; i++)
+ override_color.f32[i] = CLAMP(override_color.f32[i], 0.0f, 1.0f);
+ break;
+
+ case GL_SIGNED_NORMALIZED:
+ for (int i = 0; i < 4; i++)
+ override_color.f32[i] = CLAMP(override_color.f32[i], -1.0f, 1.0f);
+ break;
+
+ case GL_UNSIGNED_INT:
+ for (int i = 0; i < 4; i++) {
+ unsigned bits = _mesa_get_format_bits(mt->format, GL_RED_BITS + i);
+ if (bits < 32) {
+ uint32_t max = (1u << bits) - 1;
+ override_color.u32[i] = MIN2(override_color.u32[i], max);
+ }
+ }
+ break;
+
+ case GL_INT:
+ for (int i = 0; i < 4; i++) {
+ unsigned bits = _mesa_get_format_bits(mt->format, GL_RED_BITS + i);
+ if (bits < 32) {
+ int32_t max = (1 << (bits - 1)) - 1;
+ int32_t min = -(1 << (bits - 1));
+ override_color.i32[i] = CLAMP(override_color.i32[i], min, max);
+ }
+ }
+ break;
+
+ case GL_FLOAT:
+ if (!_mesa_is_format_signed(mt->format)) {
+ for (int i = 0; i < 4; i++)
+ override_color.f32[i] = MAX2(override_color.f32[i], 0.0f);
+ }
+ break;
+ }
+
if (!_mesa_format_has_color_component(mt->format, 3)) {
if (_mesa_is_format_integer_color(mt->format))
override_color.u32[3] = 1;

[Chad Versace]

Post by Jason Ekstrand
Starting with Sky Lake, we can clear to arbitrary floats or integers.
Unfortunately, the hardware isn't particularly smart when it comes
sampling from that clear color. If the clear color is out of range for
the surface format, it will happily return whatever we put in the
surface state packet unmodified. In order to avoid returning bogus
values for surfaces with a limited range, we need to do some clamping.
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)

This reminded me that GL has no GL_UNSIGNED_FLOAT.

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a1be37e..6e94ba3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -922,6 +922,8 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
return NULL;

mt->target = target;
+ mt->level[0].level_x = image->tile_x;
+ mt->level[0].level_y = image->tile_y;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
mt->total_width += image->tile_x;

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
1 file changed, 2 insertions(+)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

This is mostly a direct port. The only bit of refactoring that was done
was to make creating a planar miptree be an early return from the
non-planar case. Alternatively, we could have three functions: two
helpers and a main function to just call the right helper. Making the
planar case an early return seemed cleaner.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 91 +++++++++++++++++++++++++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
src/mesa/drivers/dri/i965/intel_tex_image.c | 97 +--------------------------
3 files changed, 97 insertions(+), 96 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 101317f..023c6aa 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -27,6 +27,7 @@
#include <GL/internal/dri_interface.h>

#include "intel_batchbuffer.h"
+#include "intel_image.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "intel_blit.h"
@@ -856,6 +857,96 @@ intel_miptree_create_for_bo(struct brw_context *brw,
return mt;
}

+static struct intel_mipmap_tree *
+miptree_create_for_planar_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ struct intel_image_format *f = image->planar_format;
+ struct intel_mipmap_tree *planar_mt;
+
+ for (int i = 0; i < f->nplanes; i++) {
+ const int index = f->planes[i].buffer_index;
+ const uint32_t dri_format = f->planes[i].dri_format;
+ const mesa_format format = driImageFormatToGLFormat(dri_format);
+ const uint32_t width = image->width >> f->planes[i].width_shift;
+ const uint32_t height = image->height >> f->planes[i].height_shift;
+
+ /* Disable creation of the texture's aux buffers because the driver
+ * exposes no EGL API to manage them. That is, there is no API for
+ * resolving the aux buffer's content to the main buffer nor for
+ * invalidating the aux buffer's content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, format,
+ image->offsets[index],
+ width, height, 1,
+ image->strides[index],
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->total_width = width;
+ mt->total_height = height;
+
+ if (i == 0)
+ planar_mt = mt;
+ else
+ planar_mt->plane[i - 1] = mt;
+ }
+
+ return planar_mt;
+}
+
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ if (image->planar_format && image->planar_format->nplanes > 0)
+ return miptree_create_for_planar_image(brw, image, target);
+
+ if (!brw->ctx.TextureFormatSupported[image->format])
+ return NULL;
+
+ /* Disable creation of the texture's aux buffers because the driver exposes
+ * no EGL API to manage them. That is, there is no API for resolving the aux
+ * buffer's content to the main buffer nor for invalidating the aux buffer's
+ * content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, image->format,
+ 0, image->width, image->height, 1,
+ image->pitch,
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->total_width = image->width;
+ mt->total_height = image->height;
+ mt->level[0].slice[0].x_offset = image->tile_x;
+ mt->level[0].slice[0].y_offset = image->tile_y;
+
+ /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
+ * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
+ * trouble resolving back to destination image due to alignment issues.
+ */
+ if (!brw->has_surface_tile_offset) {
+ uint32_t draw_x, draw_y;
+ intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
+
+ if (draw_x != 0 || draw_y != 0) {
+ _mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
+ mt->offset = image->offset;
+
+ return mt;
+}
+
/**
* For a singlesample renderbuffer, this simply wraps the given BO with a
* miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f34be9a..9b6bc40 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -696,6 +696,11 @@ intel_miptree_create_for_bo(struct brw_context *brw,
int pitch,
uint32_t layout_flags);

+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image,
+ GLenum target);
+
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index ea166f0..580e3b2 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -201,98 +201,6 @@ intel_set_texture_image_mt(struct brw_context *brw,
intel_miptree_reference(&intel_texobj->mt, mt);
}

-static struct intel_mipmap_tree *
-create_mt_for_planar_dri_image(struct brw_context *brw,
- GLenum target, __DRIimage *image)
-{
- struct intel_image_format *f = image->planar_format;
- struct intel_mipmap_tree *planar_mt;
-
- for (int i = 0; i < f->nplanes; i++) {
- const int index = f->planes[i].buffer_index;
- const uint32_t dri_format = f->planes[i].dri_format;
- const mesa_format format = driImageFormatToGLFormat(dri_format);
- const uint32_t width = image->width >> f->planes[i].width_shift;
- const uint32_t height = image->height >> f->planes[i].height_shift;
-
- /* Disable creation of the texture's aux buffers because the driver
- * exposes no EGL API to manage them. That is, there is no API for
- * resolving the aux buffer's content to the main buffer nor for
- * invalidating the aux buffer's content.
- */
- struct intel_mipmap_tree *mt =
- intel_miptree_create_for_bo(brw, image->bo, format,
- image->offsets[index],
- width, height, 1,
- image->strides[index],
- MIPTREE_LAYOUT_DISABLE_AUX);
- if (mt == NULL)
- return NULL;
-
- mt->target = target;
- mt->total_width = width;
- mt->total_height = height;
-
- if (i == 0)
- planar_mt = mt;
- else
- planar_mt->plane[i - 1] = mt;
- }
-
- return planar_mt;
-}
-
-/**
- * Binds a BO to a texture image, as if it was uploaded by glTexImage2D().
- *
- * Used for GLX_EXT_texture_from_pixmap and EGL image extensions,
- */
-static struct intel_mipmap_tree *
-create_mt_for_dri_image(struct brw_context *brw,
- GLenum target, __DRIimage *image)
-{
- struct gl_context *ctx = &brw->ctx;
- struct intel_mipmap_tree *mt;
- uint32_t draw_x, draw_y;
-
- if (!ctx->TextureFormatSupported[image->format])
- return NULL;
-
- /* Disable creation of the texture's aux buffers because the driver exposes
- * no EGL API to manage them. That is, there is no API for resolving the aux
- * buffer's content to the main buffer nor for invalidating the aux buffer's
- * content.
- */
- mt = intel_miptree_create_for_bo(brw, image->bo, image->format,
- 0, image->width, image->height, 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
- if (mt == NULL)
- return NULL;
-
- mt->target = target;
- mt->total_width = image->width;
- mt->total_height = image->height;
- mt->level[0].slice[0].x_offset = image->tile_x;
- mt->level[0].slice[0].y_offset = image->tile_y;
-
- intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
-
- /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
- * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
- * trouble resolving back to destination image due to alignment issues.
- */
- if (!brw->has_surface_tile_offset &&
- (draw_x != 0 || draw_y != 0)) {
- _mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
- intel_miptree_release(&mt);
- return NULL;
- }
-
- mt->offset = image->offset;
-
- return mt;
-}

void
intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
@@ -435,10 +343,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
return;
}

- if (image->planar_format && image->planar_format->nplanes > 0)
- mt = create_mt_for_planar_dri_image(brw, target, image);
- else
- mt = create_mt_for_dri_image(brw, target, image);
+ mt = intel_miptree_create_for_dri_image(brw, image, target);
if (mt == NULL)
return;

[Pohjolainen, Topi]

Post by Jason Ekstrand
This is mostly a direct port. The only bit of refactoring that was done
was to make creating a planar miptree be an early return from the
non-planar case. Alternatively, we could have three functions: two
helpers and a main function to just call the right helper. Making the
planar case an early return seemed cleaner.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 91 +++++++++++++++++++++++++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
src/mesa/drivers/dri/i965/intel_tex_image.c | 97 +--------------------------
3 files changed, 97 insertions(+), 96 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 101317f..023c6aa 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -27,6 +27,7 @@
#include <GL/internal/dri_interface.h>
#include "intel_batchbuffer.h"
+#include "intel_image.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "intel_blit.h"
@@ -856,6 +857,96 @@ intel_miptree_create_for_bo(struct brw_context *brw,
return mt;
}
+static struct intel_mipmap_tree *
+miptree_create_for_planar_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ struct intel_image_format *f = image->planar_format;
+ struct intel_mipmap_tree *planar_mt;
+
+ for (int i = 0; i < f->nplanes; i++) {
+ const int index = f->planes[i].buffer_index;
+ const uint32_t dri_format = f->planes[i].dri_format;
+ const mesa_format format = driImageFormatToGLFormat(dri_format);
+ const uint32_t width = image->width >> f->planes[i].width_shift;
+ const uint32_t height = image->height >> f->planes[i].height_shift;
+
+ /* Disable creation of the texture's aux buffers because the driver
+ * exposes no EGL API to manage them. That is, there is no API for
+ * resolving the aux buffer's content to the main buffer nor for
+ * invalidating the aux buffer's content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, format,
+ image->offsets[index],
+ width, height, 1,
+ image->strides[index],
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->total_width = width;
+ mt->total_height = height;
+
+ if (i == 0)
+ planar_mt = mt;
+ else
+ planar_mt->plane[i - 1] = mt;
+ }
+
+ return planar_mt;
+}
+
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ if (image->planar_format && image->planar_format->nplanes > 0)
+ return miptree_create_for_planar_image(brw, image, target);
+
+ if (!brw->ctx.TextureFormatSupported[image->format])
+ return NULL;
+
+ /* Disable creation of the texture's aux buffers because the driver exposes
+ * no EGL API to manage them. That is, there is no API for resolving the aux
+ * buffer's content to the main buffer nor for invalidating the aux buffer's
+ * content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, image->format,
+ 0, image->width, image->height, 1,
+ image->pitch,
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->total_width = image->width;
+ mt->total_height = image->height;
+ mt->level[0].slice[0].x_offset = image->tile_x;
+ mt->level[0].slice[0].y_offset = image->tile_y;
+
+ /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
+ * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
+ * trouble resolving back to destination image due to alignment issues.
+ */
+ if (!brw->has_surface_tile_offset) {
+ uint32_t draw_x, draw_y;
+ intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
+
+ if (draw_x != 0 || draw_y != 0) {
+ _mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
+ mt->offset = image->offset;
+
+ return mt;
+}
+
/**
* For a singlesample renderbuffer, this simply wraps the given BO with a
* miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f34be9a..9b6bc40 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -696,6 +696,11 @@ intel_miptree_create_for_bo(struct brw_context *brw,
int pitch,
uint32_t layout_flags);
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image,
+ GLenum target);
+
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index ea166f0..580e3b2 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -201,98 +201,6 @@ intel_set_texture_image_mt(struct brw_context *brw,
intel_miptree_reference(&intel_texobj->mt, mt);
}
-static struct intel_mipmap_tree *
-create_mt_for_planar_dri_image(struct brw_context *brw,
- GLenum target, __DRIimage *image)
-{
- struct intel_image_format *f = image->planar_format;
- struct intel_mipmap_tree *planar_mt;
-
- for (int i = 0; i < f->nplanes; i++) {
- const int index = f->planes[i].buffer_index;
- const uint32_t dri_format = f->planes[i].dri_format;
- const mesa_format format = driImageFormatToGLFormat(dri_format);
- const uint32_t width = image->width >> f->planes[i].width_shift;
- const uint32_t height = image->height >> f->planes[i].height_shift;
-
- /* Disable creation of the texture's aux buffers because the driver
- * exposes no EGL API to manage them. That is, there is no API for
- * resolving the aux buffer's content to the main buffer nor for
- * invalidating the aux buffer's content.
- */
- struct intel_mipmap_tree *mt =
- intel_miptree_create_for_bo(brw, image->bo, format,
- image->offsets[index],
- width, height, 1,
- image->strides[index],
- MIPTREE_LAYOUT_DISABLE_AUX);
- if (mt == NULL)
- return NULL;
-
- mt->target = target;
- mt->total_width = width;
- mt->total_height = height;
-
- if (i == 0)
- planar_mt = mt;
- else
- planar_mt->plane[i - 1] = mt;
- }
-
- return planar_mt;
-}
-
-/**
- * Binds a BO to a texture image, as if it was uploaded by glTexImage2D().
- *
- * Used for GLX_EXT_texture_from_pixmap and EGL image extensions,
- */
-static struct intel_mipmap_tree *
-create_mt_for_dri_image(struct brw_context *brw,
- GLenum target, __DRIimage *image)
-{
- struct gl_context *ctx = &brw->ctx;
- struct intel_mipmap_tree *mt;
- uint32_t draw_x, draw_y;
-
- if (!ctx->TextureFormatSupported[image->format])
- return NULL;
-
- /* Disable creation of the texture's aux buffers because the driver exposes
- * no EGL API to manage them. That is, there is no API for resolving the aux
- * buffer's content to the main buffer nor for invalidating the aux buffer's
- * content.
- */
- mt = intel_miptree_create_for_bo(brw, image->bo, image->format,
- 0, image->width, image->height, 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
- if (mt == NULL)
- return NULL;
-
- mt->target = target;
- mt->total_width = image->width;
- mt->total_height = image->height;
- mt->level[0].slice[0].x_offset = image->tile_x;
- mt->level[0].slice[0].y_offset = image->tile_y;
-
- intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
-
- /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
- * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
- * trouble resolving back to destination image due to alignment issues.
- */
- if (!brw->has_surface_tile_offset &&
- (draw_x != 0 || draw_y != 0)) {
- _mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
- intel_miptree_release(&mt);
- return NULL;
- }
-
- mt->offset = image->offset;
-
- return mt;
-}
void
intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
@@ -435,10 +343,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
return;
}
- if (image->planar_format && image->planar_format->nplanes > 0)
- mt = create_mt_for_planar_dri_image(brw, target, image);
- else
- mt = create_mt_for_dri_image(brw, target, image);
+ mt = intel_miptree_create_for_dri_image(brw, image, target);
if (mt == NULL)
return;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Jason Ekstrand
This is mostly a direct port. The only bit of refactoring that was done
was to make creating a planar miptree be an early return from the
non-planar case. Alternatively, we could have three functions: two
helpers and a main function to just call the right helper. Making the
planar case an early return seemed cleaner.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 91 +++++++++++++++++++++++++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
src/mesa/drivers/dri/i965/intel_tex_image.c | 97 +--------------------------
3 files changed, 97 insertions(+), 96 deletions(-)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

This is what we do in intel_image_target_renderbuffer_storage and it
makes more sense than stomping them. Because the image gets created as
a 2D image with one miplevel, they should already be equal to the
provided width/height. Adding the tile offset makes some sense
depending on how you interpret the fields. Also, they're never used for
any sort of state setup so I don't think it really matters anyway.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3bc6827..a1be37e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -922,10 +922,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
return NULL;

mt->target = target;
- mt->total_width = image->width;
- mt->total_height = image->height;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
+ mt->total_width += image->tile_x;
+ mt->total_height += image->tile_y;

/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has

[Chad Versace]

Post by Jason Ekstrand
This is what we do in intel_image_target_renderbuffer_storage and it
makes more sense than stomping them. Because the image gets created as
a 2D image with one miplevel, they should already be equal to the
provided width/height. Adding the tile offset makes some sense
depending on how you interpret the fields. Also, they're never used for
any sort of state setup so I don't think it really matters anyway.
---

mt->total_height *is* used for state setup, for calculating qpitch in
brw_miptree_get_vertical_slice_pitch(), which is transitively called
from brw_upload_image_surfaces().

mt->total_width is never used for miptrees created for DRIimage's, as
far as I can tell.

Regardless, I believe that all code that accesses
DRIimage::offset,tile_x,tile_y is horribly broken, and this patch
accordingly does not alter the entropy.

For consistency with intel_image_target_renderbuffer_storage(), and no
other reason, this patch is
Reviewed-by: Chad Versace <***@chromium.org>

Please update the commit message to mention that at least
mt->total_width is used.

Post by Jason Ekstrand
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3bc6827..a1be37e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -922,10 +922,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
return NULL;
mt->target = target;
- mt->total_width = image->width;
- mt->total_height = image->height;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
+ mt->total_width += image->tile_x;
+ mt->total_height += image->tile_y;
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.

This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 +++++++++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
can_fast_clear = false;

- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
can_fast_clear = false;

@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to recover
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,

intel_renderbuffer_set_draw_offset(irb);

- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
return false;

- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return true;
}

+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ case MESA_FORMAT_Z_FLOAT32:
+ case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+ case MESA_FORMAT_Z24_UNORM_X8_UINT:
+ case MESA_FORMAT_Z24_UNORM_S8_UINT:
+ case MESA_FORMAT_Z_UNORM16:
+ return true;
+ default:
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, mt->aux_disable);
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw, mt)))) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context *brw,
return NULL;
}

- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}


/**
+ * Choose the aux usage for this miptree. This function must be called fairly
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
+/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
*/
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;

+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}

@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
}
}

- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create the CCS
+ * for it up-front. For CCS_D which only compresses clears, we create the
+ * CCS on-demand when a clear occurs that wants one.
*/
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming compressed
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}
}

@@ -805,6 +838,21 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->offset = offset;
mt->tiling = tiling;

+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
return mt;
}

@@ -849,16 +897,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
if (!singlesample_mt)
goto fail;

- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -913,7 +951,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
if (!mt)
goto fail;

- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1492,7 +1530,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);

/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1551,11 +1589,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,

bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);

struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
@@ -1590,7 +1628,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;

buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1607,7 +1646,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
@@ -1868,36 +1907,11 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
}

bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- case MESA_FORMAT_Z_FLOAT32:
- case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
- case MESA_FORMAT_Z24_UNORM_X8_UINT:
- case MESA_FORMAT_Z24_UNORM_S8_UINT:
- case MESA_FORMAT_Z_UNORM16:
- return true;
- default:
- return false;
- }
-}
-
-bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);

enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
@@ -2016,7 +2030,7 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
unsigned level, unsigned layer)
{

- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;

/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
@@ -2645,7 +2659,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
0, INTEL_REMAINING_LAYERS, false, false);

if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
@@ -2659,7 +2672,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
}

if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;

@@ -2674,6 +2686,8 @@ intel_miptree_make_shareable(struct brw_context *brw,
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}


@@ -3716,17 +3730,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;

- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
+ *usage = mt->aux_usage;
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index aa33967..f34be9a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -287,16 +287,6 @@ enum miptree_array_layout {
GEN6_HIZ_STENCIL,
};

-enum intel_aux_disable {
- INTEL_AUX_DISABLE_NONE = 0,
- INTEL_AUX_DISABLE_HIZ = 1 << 1,
- INTEL_AUX_DISABLE_MCS = 1 << 2,
- INTEL_AUX_DISABLE_CCS = 1 << 3,
- INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
- INTEL_AUX_DISABLE_MCS |
- INTEL_AUX_DISABLE_CCS
-};
-
/**
* Miptree aux buffer. These buffers are associated with a miptree, but the
* format is managed by the hardware.
@@ -576,6 +566,25 @@ struct intel_mipmap_tree
struct intel_miptree_hiz_buffer *hiz_buf;

/**
+ * \brief The type of auxiliary compression used by this miptree.
+ *
+ * This describes the type of auxiliary compression that is intended to be
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
+ * auxiliary compression is permanently disabled. An aux usage other than
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
+ * been allocated nor does it imply that auxiliary compression will always
+ * be enabled for this surface. For instance, with CCS_D, we may allocate
+ * the CCS on-the-fly and it may not be used for texturing if the miptree
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
* \brief Maps miptree slices to their current aux state
*
* This two-dimensional array is indexed as [level][layer] and stores an
@@ -631,13 +640,6 @@ struct intel_mipmap_tree
union isl_color_value fast_clear_color;

/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
- * buffer. This is useful for sharing the miptree bo with an external client
- * that doesn't understand auxiliary buffers.
- */
- enum intel_aux_disable aux_disable;
-
- /**
* Tells if the underlying buffer is to be also consumed by entities other
* than the driver. This allows logic to turn off features such as lossless
* compression which is not currently understood by client applications.
@@ -655,8 +657,7 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,

bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e);
+ struct intel_mipmap_tree *mt);

enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
@@ -814,10 +815,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
* functions on a miptree without HiZ. In that case, each function is a no-op.
*/

-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt

[Pohjolainen, Topi]

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 +++++++++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
can_fast_clear = false;
- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to recover
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
intel_renderbuffer_set_draw_offset(irb);
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
return false;
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return true;
}
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ return true;
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, mt->aux_disable);
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
* "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw, mt)))) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context *brw,
return NULL;
}
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}
/**
+ * Choose the aux usage for this miptree. This function must be called fairly
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&

In the commit message you said that this patch enables CCS_E for winsys
buffers. I don't see how that happens as we check for is_scanout here (which
gets set by intel_miptree_create_layout() by
intel_update_winsys_renderbuffer_miptree() passing MIPTREE_LAYOUT_FOR_SCANOUT).

Post by Jason Ekstrand
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
+/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
*/
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}
@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
}
}
- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create the CCS
+ * for it up-front. For CCS_D which only compresses clears, we create the
+ * CCS on-demand when a clear occurs that wants one.
*/
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming compressed
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}
}
@@ -805,6 +838,21 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->offset = offset;
mt->tiling = tiling;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
return mt;
}
@@ -849,16 +897,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
if (!singlesample_mt)
goto fail;
- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -913,7 +951,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
if (!mt)
goto fail;
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1492,7 +1530,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1551,11 +1589,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);
struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
@@ -1590,7 +1628,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1607,7 +1646,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
@@ -1868,36 +1907,11 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
}
bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- return true;
- return false;
- }
-}
-
-bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
@@ -2016,7 +2030,7 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
unsigned level, unsigned layer)
{
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
@@ -2645,7 +2659,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
0, INTEL_REMAINING_LAYERS, false, false);
if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
@@ -2659,7 +2672,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
}
if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
@@ -2674,6 +2686,8 @@ intel_miptree_make_shareable(struct brw_context *brw,
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}
@@ -3716,17 +3730,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
+ *usage = mt->aux_usage;
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index aa33967..f34be9a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -287,16 +287,6 @@ enum miptree_array_layout {
GEN6_HIZ_STENCIL,
};
-enum intel_aux_disable {
- INTEL_AUX_DISABLE_NONE = 0,
- INTEL_AUX_DISABLE_HIZ = 1 << 1,
- INTEL_AUX_DISABLE_MCS = 1 << 2,
- INTEL_AUX_DISABLE_CCS = 1 << 3,
- INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
- INTEL_AUX_DISABLE_MCS |
- INTEL_AUX_DISABLE_CCS
-};
-
/**
* Miptree aux buffer. These buffers are associated with a miptree, but the
* format is managed by the hardware.
@@ -576,6 +566,25 @@ struct intel_mipmap_tree
struct intel_miptree_hiz_buffer *hiz_buf;
/**
+ * \brief The type of auxiliary compression used by this miptree.
+ *
+ * This describes the type of auxiliary compression that is intended to be
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
+ * auxiliary compression is permanently disabled. An aux usage other than
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
+ * been allocated nor does it imply that auxiliary compression will always
+ * be enabled for this surface. For instance, with CCS_D, we may allocate
+ * the CCS on-the-fly and it may not be used for texturing if the miptree
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
* \brief Maps miptree slices to their current aux state
*
* This two-dimensional array is indexed as [level][layer] and stores an
@@ -631,13 +640,6 @@ struct intel_mipmap_tree
union isl_color_value fast_clear_color;
/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
- * buffer. This is useful for sharing the miptree bo with an external client
- * that doesn't understand auxiliary buffers.
- */
- enum intel_aux_disable aux_disable;
-
- /**
* Tells if the underlying buffer is to be also consumed by entities other
* than the driver. This allows logic to turn off features such as lossless
* compression which is not currently understood by client applications.
@@ -655,8 +657,7 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e);
+ struct intel_mipmap_tree *mt);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
@@ -814,10 +815,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
* functions on a miptree without HiZ. In that case, each function is a no-op.
*/
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

On Wed, Jun 21, 2017 at 5:35 AM, Pohjolainen, Topi <

Post by Jason Ekstrand

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190

+++++++++++++-------------

Post by Jason Ekstrand
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

b/src/mesa/drivers/dri/i965/brw_blorp.c

Post by Jason Ekstrand
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw,

struct gl_framebuffer *fb,

Post by Jason Ekstrand
if (set_write_disables(irb, ctx->Color.ColorMask[buf],

color_write_disable))

Post by Jason Ekstrand
can_fast_clear = false;
- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt,

&ctx->Color.ClearColor))

Post by Jason Ekstrand
can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw,

struct gl_framebuffer *fb,

Post by Jason Ekstrand
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to

recover

Post by Jason Ekstrand
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c

b/src/mesa/drivers/dri/i965/intel_fbo.c

Post by Jason Ekstrand
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct

brw_context *brw,

Post by Jason Ekstrand
intel_renderbuffer_set_draw_offset(irb);
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

Post by Jason Ekstrand
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,

mesa_format format,

Post by Jason Ekstrand
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) ==

GL_INT) {

Post by Jason Ekstrand
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer,

the MCS

Post by Jason Ekstrand
* buffer. So fallback to UMS, which is identical to CMS

without the

Post by Jason Ekstrand
* MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
return false;
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return true;
}
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ return true;
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context

*brw,

Post by Jason Ekstrand
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format,

mt->aux_disable);

Post by Jason Ekstrand
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
* "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw,

mt)))) {

Post by Jason Ekstrand
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context

*brw,

Post by Jason Ekstrand
return NULL;
}
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}
/**
+ * Choose the aux usage for this miptree. This function must be called

fairly

Post by Jason Ekstrand
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&

In the commit message you said that this patch enables CCS_E for winsys
buffers. I don't see how that happens as we check for is_scanout here (which
gets set by intel_miptree_create_layout() by
intel_update_winsys_renderbuffer_miptree() passing
MIPTREE_LAYOUT_FOR_SCANOUT).

Well... It gets us closer at any rate. More work to do there. I'll update
the commit message to not claim to actually fix the issue.

Post by Jason Ekstrand

Post by Jason Ekstrand
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
+/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
*/
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}
@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
}
}
- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will

occur.

Post by Jason Ekstrand
- * Allocation of the MCS miptree will be deferred until the first

fast

Post by Jason Ekstrand
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create

the CCS

Post by Jason Ekstrand
+ * for it up-front. For CCS_D which only compresses clears, we

create the

Post by Jason Ekstrand
+ * CCS on-demand when a clear occurs that wants one.
*/
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming

compressed

Post by Jason Ekstrand
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG &

DEBUG_NO_RBC;

Post by Jason Ekstrand
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}
}
@@ -805,6 +838,21 @@ intel_miptree_create_for_bo(struct brw_context

*brw,

Post by Jason Ekstrand
mt->offset = offset;
mt->tiling = tiling;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create

the

Post by Jason Ekstrand
+ * CCS for it up-front. For CCS_D which only compresses clears,

we

Post by Jason Ekstrand
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
return mt;
}
@@ -849,16 +897,6 @@ intel_update_winsys_renderbuffer_miptree(struct

brw_context *intel,

Post by Jason Ekstrand
if (!singlesample_mt)
goto fail;
- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first

fast

Post by Jason Ekstrand
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -913,7 +951,7 @@ intel_miptree_create_for_renderbuffer(struct

brw_context *brw,

Post by Jason Ekstrand
if (!mt)
goto fail;
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1492,7 +1530,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
/* Choose the correct format for the MCS buffer. All that really

matters

Post by Jason Ekstrand
* is that we allocate the right buffer size, since we'll always be
@@ -1551,11 +1589,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS |

INTEL_AUX_DISABLE_CCS)));

Post by Jason Ekstrand
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);
struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
@@ -1590,7 +1628,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay

if the

Post by Jason Ekstrand
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1607,7 +1646,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* used for lossless compression which requires similar

initialisation

Post by Jason Ekstrand
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does

full

Post by Jason Ekstrand
* resolve. Initialize it accordingly in case the first renderer

is

Post by Jason Ekstrand
* cpu (or other none compression aware party).
@@ -1868,36 +1907,11 @@ intel_hiz_miptree_buf_create(struct brw_context

*brw,

Post by Jason Ekstrand
}
bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- return true;
- return false;
- }
-}
-
-bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
@@ -2016,7 +2030,7 @@ intel_miptree_check_color_resolve(const struct

brw_context *brw,

Post by Jason Ekstrand
unsigned level, unsigned layer)
{
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on

Gen8+. */

Post by Jason Ekstrand
@@ -2645,7 +2659,6 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
0, INTEL_REMAINING_LAYERS, false,

false);

Post by Jason Ekstrand
if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS |

INTEL_AUX_DISABLE_MCS);

Post by Jason Ekstrand
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
@@ -2659,7 +2672,6 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
}
if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
@@ -2674,6 +2686,8 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}
@@ -3716,17 +3730,7 @@ intel_miptree_get_aux_isl_surf(struct

brw_context *brw,

Post by Jason Ekstrand
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
+ *usage = mt->aux_usage;
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h

b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h

Post by Jason Ekstrand
index aa33967..f34be9a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -287,16 +287,6 @@ enum miptree_array_layout {
GEN6_HIZ_STENCIL,
};
-enum intel_aux_disable {
- INTEL_AUX_DISABLE_NONE = 0,
- INTEL_AUX_DISABLE_HIZ = 1 << 1,
- INTEL_AUX_DISABLE_MCS = 1 << 2,
- INTEL_AUX_DISABLE_CCS = 1 << 3,
- INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
- INTEL_AUX_DISABLE_MCS |
- INTEL_AUX_DISABLE_CCS
-};
-
/**
* Miptree aux buffer. These buffers are associated with a miptree, but

the

Post by Jason Ekstrand
* format is managed by the hardware.
@@ -576,6 +566,25 @@ struct intel_mipmap_tree
struct intel_miptree_hiz_buffer *hiz_buf;
/**
+ * \brief The type of auxiliary compression used by this miptree.
+ *
+ * This describes the type of auxiliary compression that is intended

to be

Post by Jason Ekstrand
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means

that

Post by Jason Ekstrand
+ * auxiliary compression is permanently disabled. An aux usage

other than

Post by Jason Ekstrand
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has

actually

Post by Jason Ekstrand
+ * been allocated nor does it imply that auxiliary compression will

always

Post by Jason Ekstrand
+ * be enabled for this surface. For instance, with CCS_D, we may

allocate

Post by Jason Ekstrand
+ * the CCS on-the-fly and it may not be used for texturing if the

miptree

Post by Jason Ekstrand
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
* \brief Maps miptree slices to their current aux state
*
* This two-dimensional array is indexed as [level][layer] and

stores an

Post by Jason Ekstrand
@@ -631,13 +640,6 @@ struct intel_mipmap_tree
union isl_color_value fast_clear_color;
/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer

and MCS

Post by Jason Ekstrand
- * buffer. This is useful for sharing the miptree bo with an

external client

Post by Jason Ekstrand
- * that doesn't understand auxiliary buffers.
- */
- enum intel_aux_disable aux_disable;
-
- /**
* Tells if the underlying buffer is to be also consumed by entities

other

Post by Jason Ekstrand
* than the driver. This allows logic to turn off features such as

lossless

Post by Jason Ekstrand
* compression which is not currently understood by client

applications.

Post by Jason Ekstrand
@@ -655,8 +657,7 @@ intel_miptree_is_lossless_compressed(const struct

brw_context *brw,

Post by Jason Ekstrand
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e);
+ struct intel_mipmap_tree *mt);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
@@ -814,10 +815,6 @@ intel_miptree_copy_teximage(struct brw_context

*brw,

Post by Jason Ekstrand
* functions on a miptree without HiZ. In that case, each function is a

no-op.

Post by Jason Ekstrand
*/
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 +++++++++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
can_fast_clear = false;
- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to recover
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
intel_renderbuffer_set_draw_offset(irb);
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
return false;
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return true;
}
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ return true;
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, mt->aux_disable);
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
* "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw, mt)))) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context *brw,
return NULL;
}
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}
/**
+ * Choose the aux usage for this miptree. This function must be called fairly
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
+/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
*/
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}
@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
}
}
- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create the CCS
+ * for it up-front. For CCS_D which only compresses clears, we create the
+ * CCS on-demand when a clear occurs that wants one.
*/

The above comment...

Post by Jason Ekstrand
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming compressed
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}

...and the above hunk appear twice in the commit. I believe that both
locations are necessary and sufficient. However, you can replace them
with a single location.

Also, the patch contains two calls to intel_miptree_choose_aux_usage().
Again, you can replace them with a single call.

Intstead of having these two things duplicated, I think they should
each happen once along the common code path:
intel_miptree_create_layout(). That should lead to less fragile code,
I hope.

Facts:

* All miptree creation paths eventually lead to
intel_miptree_create_layout().

* The result of intel_miptree_choose_aux_usage() depends directly on
mt->msaa_layout and indirectly on mt->tiling. As far as I can
tell, it depends on no other miptree state.

* mt->msaa_layout is set in exactly two places: the top of
intel_miptree_create_layout() and as a side-effect of
intel_miptree_alloc_ccs(). (Why intel_miptree_alloc_ccs, formerly
intel_miptree_alloc_non_msrt_mcs, sets mt->msaa_layout to
INTEL_MSAA_LAYOUT_CMS is a mystery to me. I choose to ignore it,
because I suspect that assignment is nowhere used afterwards.
WARNING: I have left the realm of facts!)

* mt->tiling is set in exactly 3 locations in intel_mipmap_tree.c:

a. intel_miptree_create_layout() sometimes sets mt->tiling as one of its
last actions, when it calls brw_miptree_layout(). "sometimes",
because brw_miptree_layout() sets mt->tiling if and only if
!MIPTREE_LAYOUT_FOR_BO.

b. intel_miptree_create_for_bo() sets mt->tiling immediately
after calling intel_miptree_create_layout().

c. miptree_create() sets mt->tiling in a weird fallback
immediately after it calls intel_miptree_create_layout().

Conclusions:

* You can collapse the two calls of
intel_miptree_choose_aux_usage(), and the two pre-allocations of
the ccs_e, into a single location (which I'll call "pot o' gold")
at the tail of intel_miptree_create_layout() immediately before it
returns, IF...

* IF the pot o' gold happens after mt->msaa_layout is set. This
is trivial because mt->msaa_layout is set at the top of
intel_miptree_create_layout() and nowhere else, modulo my
willfull ignorance of intel_miptree_alloc_ccs's weirdness.

* IF the pot o' gold happens after mt->tiling is set. What's
required for this is:

* Move the mt->tiling assignment in (b)
to occur immediately before the call to intel_miptree_create_layout().
Trivial fixup.

* Fix the weird tiling fallback in item (c) by pushing it into
intel_miptree_create_layout(). Another trivial fixup.


I expect that I missed some details. I await your rebuttal.

Post by Jason Ekstrand
}
@@ -805,6 +838,21 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->offset = offset;
mt->tiling = tiling;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
return mt;
}
@@ -849,16 +897,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
if (!singlesample_mt)
goto fail;
- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -913,7 +951,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
if (!mt)
goto fail;
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1492,7 +1530,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1551,11 +1589,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);
struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
@@ -1590,7 +1628,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1607,7 +1646,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
@@ -1868,36 +1907,11 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
}
bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- return true;
- return false;
- }
-}
-
-bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
@@ -2016,7 +2030,7 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
unsigned level, unsigned layer)
{
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
@@ -2645,7 +2659,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
0, INTEL_REMAINING_LAYERS, false, false);
if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
@@ -2659,7 +2672,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
}
if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
@@ -2674,6 +2686,8 @@ intel_miptree_make_shareable(struct brw_context *brw,
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}
@@ -3716,17 +3730,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
+ *usage = mt->aux_usage;
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index aa33967..f34be9a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -287,16 +287,6 @@ enum miptree_array_layout {
GEN6_HIZ_STENCIL,
};
-enum intel_aux_disable {
- INTEL_AUX_DISABLE_NONE = 0,
- INTEL_AUX_DISABLE_HIZ = 1 << 1,
- INTEL_AUX_DISABLE_MCS = 1 << 2,
- INTEL_AUX_DISABLE_CCS = 1 << 3,
- INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
- INTEL_AUX_DISABLE_MCS |
- INTEL_AUX_DISABLE_CCS
-};
-
/**
* Miptree aux buffer. These buffers are associated with a miptree, but the
* format is managed by the hardware.
@@ -576,6 +566,25 @@ struct intel_mipmap_tree
struct intel_miptree_hiz_buffer *hiz_buf;
/**
+ * \brief The type of auxiliary compression used by this miptree.
+ *
+ * This describes the type of auxiliary compression that is intended to be
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
+ * auxiliary compression is permanently disabled. An aux usage other than
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
+ * been allocated nor does it imply that auxiliary compression will always
+ * be enabled for this surface. For instance, with CCS_D, we may allocate
+ * the CCS on-the-fly and it may not be used for texturing if the miptree
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
* \brief Maps miptree slices to their current aux state
*
* This two-dimensional array is indexed as [level][layer] and stores an
@@ -631,13 +640,6 @@ struct intel_mipmap_tree
union isl_color_value fast_clear_color;
/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
- * buffer. This is useful for sharing the miptree bo with an external client
- * that doesn't understand auxiliary buffers.
- */
- enum intel_aux_disable aux_disable;
-
- /**
* Tells if the underlying buffer is to be also consumed by entities other
* than the driver. This allows logic to turn off features such as lossless
* compression which is not currently understood by client applications.
@@ -655,8 +657,7 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e);
+ struct intel_mipmap_tree *mt);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
@@ -814,10 +815,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
* functions on a miptree without HiZ. In that case, each function is a no-op.
*/
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

Post by Jason Ekstrand

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190

+++++++++++++-------------

Post by Jason Ekstrand
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

b/src/mesa/drivers/dri/i965/brw_blorp.c

Post by Jason Ekstrand
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw,

struct gl_framebuffer *fb,

Post by Jason Ekstrand
if (set_write_disables(irb, ctx->Color.ColorMask[buf],

color_write_disable))

Post by Jason Ekstrand
can_fast_clear = false;
- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt,

&ctx->Color.ClearColor))

Post by Jason Ekstrand
can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw,

struct gl_framebuffer *fb,

Post by Jason Ekstrand
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* MCS allocation failed--probably this will only happen in
* out-of-memory conditions. But in any case, try to

recover

Post by Jason Ekstrand
* by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c

b/src/mesa/drivers/dri/i965/intel_fbo.c

Post by Jason Ekstrand
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct

brw_context *brw,

Post by Jason Ekstrand
intel_renderbuffer_set_draw_offset(irb);
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

Post by Jason Ekstrand
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,

mesa_format format,

Post by Jason Ekstrand
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) ==

GL_INT) {

Post by Jason Ekstrand
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer,

the MCS

Post by Jason Ekstrand
* buffer. So fallback to UMS, which is identical to CMS

without the

Post by Jason Ekstrand
* MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
return false;
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return true;
}
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ return true;
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context

*brw,

Post by Jason Ekstrand
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format,

mt->aux_disable);

Post by Jason Ekstrand
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
* "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw,

mt)))) {

Post by Jason Ekstrand
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context

*brw,

Post by Jason Ekstrand
return NULL;
}
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}
/**
+ * Choose the aux usage for this miptree. This function must be called

fairly

Post by Jason Ekstrand
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
+/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
*/
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}
@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
}
}
- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will

occur.

Post by Jason Ekstrand
- * Allocation of the MCS miptree will be deferred until the first

fast

Post by Jason Ekstrand
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create

the CCS

Post by Jason Ekstrand
+ * for it up-front. For CCS_D which only compresses clears, we

create the

Post by Jason Ekstrand
+ * CCS on-demand when a clear occurs that wants one.
*/

The above comment...

Post by Jason Ekstrand
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming

compressed

Post by Jason Ekstrand
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG &

DEBUG_NO_RBC;

Post by Jason Ekstrand
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}

...and the above hunk appear twice in the commit. I believe that both
locations are necessary and sufficient. However, you can replace them
with a single location.
Also, the patch contains two calls to intel_miptree_choose_aux_usage().
Again, you can replace them with a single call.
Intstead of having these two things duplicated, I think they should
intel_miptree_create_layout(). That should lead to less fragile code,
I hope.
* All miptree creation paths eventually lead to
intel_miptree_create_layout().
* The result of intel_miptree_choose_aux_usage() depends directly on
mt->msaa_layout and indirectly on mt->tiling. As far as I can
tell, it depends on no other miptree state.
* mt->msaa_layout is set in exactly two places: the top of
intel_miptree_create_layout() and as a side-effect of
intel_miptree_alloc_ccs(). (Why intel_miptree_alloc_ccs, formerly
intel_miptree_alloc_non_msrt_mcs, sets mt->msaa_layout to
INTEL_MSAA_LAYOUT_CMS is a mystery to me. I choose to ignore it,
because I suspect that assignment is nowhere used afterwards.
WARNING: I have left the realm of facts!)
a. intel_miptree_create_layout() sometimes sets mt->tiling as one of its
last actions, when it calls brw_miptree_layout(). "sometimes",
because brw_miptree_layout() sets mt->tiling if and only if
!MIPTREE_LAYOUT_FOR_BO.
b. intel_miptree_create_for_bo() sets mt->tiling immediately
after calling intel_miptree_create_layout().
c. miptree_create() sets mt->tiling in a weird fallback
immediately after it calls intel_miptree_create_layout().
* You can collapse the two calls of
intel_miptree_choose_aux_usage(), and the two pre-allocations of
the ccs_e, into a single location (which I'll call "pot o' gold")
at the tail of intel_miptree_create_layout() immediately before it
returns, IF...
* IF the pot o' gold happens after mt->msaa_layout is set. This
is trivial because mt->msaa_layout is set at the top of
intel_miptree_create_layout() and nowhere else, modulo my
willfull ignorance of intel_miptree_alloc_ccs's weirdness.
* IF the pot o' gold happens after mt->tiling is set. What's
* Move the mt->tiling assignment in (b)
to occur immediately before the call to
intel_miptree_create_layout().
Trivial fixup.
* Fix the weird tiling fallback in item (c) by pushing it into
intel_miptree_create_layout(). Another trivial fixup.
I expect that I missed some details. I await your rebuttal.

You are correct that they could be placed on the common path, sort of. You
are wrong that it's a good idea. Why? Modifiers. With modifiers, we have
to override the choice of aux and create the auxiliary surface ourselves so
we don't want it created for us. But we also can't create it with
DISABLE_AUX because we may want it to still do HALIGN16 if we're going to
create one ourselves. So, instead, what we do is to let create_for_bo go
ahead and choose aux usage, then we stomp it to what we want, and then we
set up the CCS. We could choose aux usage in create_layout but I figured
that would hint that aux usage was something entirely chose by
create_layout and not stompped later. I don't like to imply that.

--Jason

Post by Jason Ekstrand

Post by Jason Ekstrand
}
@@ -805,6 +838,21 @@ intel_miptree_create_for_bo(struct brw_context

*brw,

Post by Jason Ekstrand
mt->offset = offset;
mt->tiling = tiling;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create

the

Post by Jason Ekstrand
+ * CCS for it up-front. For CCS_D which only compresses clears,

we

Post by Jason Ekstrand
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
return mt;
}
@@ -849,16 +897,6 @@ intel_update_winsys_renderbuffer_miptree(struct

brw_context *intel,

Post by Jason Ekstrand
if (!singlesample_mt)
goto fail;
- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first

fast

Post by Jason Ekstrand
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -913,7 +951,7 @@ intel_miptree_create_for_renderbuffer(struct

brw_context *brw,

Post by Jason Ekstrand
if (!mt)
goto fail;
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1492,7 +1530,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
/* Choose the correct format for the MCS buffer. All that really

matters

Post by Jason Ekstrand
* is that we allocate the right buffer size, since we'll always be
@@ -1551,11 +1589,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS |

INTEL_AUX_DISABLE_CCS)));

Post by Jason Ekstrand
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);
struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
@@ -1590,7 +1628,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* not use the gpu access flag which can cause an unnecessary delay

if the

Post by Jason Ekstrand
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
I915_TILING_Y, buf->pitch, alloc_flags);
@@ -1607,7 +1646,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* used for lossless compression which requires similar

initialisation

Post by Jason Ekstrand
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does

full

Post by Jason Ekstrand
* resolve. Initialize it accordingly in case the first renderer

is

Post by Jason Ekstrand
* cpu (or other none compression aware party).
@@ -1868,36 +1907,11 @@ intel_hiz_miptree_buf_create(struct brw_context

*brw,

Post by Jason Ekstrand
}
bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- return true;
- return false;
- }
-}
-
-bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
@@ -2016,7 +2030,7 @@ intel_miptree_check_color_resolve(const struct

brw_context *brw,

Post by Jason Ekstrand
unsigned level, unsigned layer)
{
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on

Gen8+. */

Post by Jason Ekstrand
@@ -2645,7 +2659,6 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
0, INTEL_REMAINING_LAYERS, false,

false);

Post by Jason Ekstrand
if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS |

INTEL_AUX_DISABLE_MCS);

Post by Jason Ekstrand
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
@@ -2659,7 +2672,6 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
}
if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_hiz_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
@@ -2674,6 +2686,8 @@ intel_miptree_make_shareable(struct brw_context

*brw,

Post by Jason Ekstrand
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}
@@ -3716,17 +3730,7 @@ intel_miptree_get_aux_isl_surf(struct

brw_context *brw,

Post by Jason Ekstrand
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
+ *usage = mt->aux_usage;
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h

b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h

Post by Jason Ekstrand
index aa33967..f34be9a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -287,16 +287,6 @@ enum miptree_array_layout {
GEN6_HIZ_STENCIL,
};
-enum intel_aux_disable {
- INTEL_AUX_DISABLE_NONE = 0,
- INTEL_AUX_DISABLE_HIZ = 1 << 1,
- INTEL_AUX_DISABLE_MCS = 1 << 2,
- INTEL_AUX_DISABLE_CCS = 1 << 3,
- INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
- INTEL_AUX_DISABLE_MCS |
- INTEL_AUX_DISABLE_CCS
-};
-
/**
* Miptree aux buffer. These buffers are associated with a miptree, but

the

Post by Jason Ekstrand
* format is managed by the hardware.
@@ -576,6 +566,25 @@ struct intel_mipmap_tree
struct intel_miptree_hiz_buffer *hiz_buf;
/**
+ * \brief The type of auxiliary compression used by this miptree.
+ *
+ * This describes the type of auxiliary compression that is intended

to be

Post by Jason Ekstrand
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means

that

Post by Jason Ekstrand
+ * auxiliary compression is permanently disabled. An aux usage

other than

Post by Jason Ekstrand
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has

actually

Post by Jason Ekstrand
+ * been allocated nor does it imply that auxiliary compression will

always

Post by Jason Ekstrand
+ * be enabled for this surface. For instance, with CCS_D, we may

allocate

Post by Jason Ekstrand
+ * the CCS on-the-fly and it may not be used for texturing if the

miptree

Post by Jason Ekstrand
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
* \brief Maps miptree slices to their current aux state
*
* This two-dimensional array is indexed as [level][layer] and

stores an

Post by Jason Ekstrand
@@ -631,13 +640,6 @@ struct intel_mipmap_tree
union isl_color_value fast_clear_color;
/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer

and MCS

Post by Jason Ekstrand
- * buffer. This is useful for sharing the miptree bo with an

external client

Post by Jason Ekstrand
- * that doesn't understand auxiliary buffers.
- */
- enum intel_aux_disable aux_disable;
-
- /**
* Tells if the underlying buffer is to be also consumed by entities

other

Post by Jason Ekstrand
* than the driver. This allows logic to turn off features such as

lossless

Post by Jason Ekstrand
* compression which is not currently understood by client

applications.

Post by Jason Ekstrand
@@ -655,8 +657,7 @@ intel_miptree_is_lossless_compressed(const struct

brw_context *brw,

Post by Jason Ekstrand
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e);
+ struct intel_mipmap_tree *mt);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
@@ -814,10 +815,6 @@ intel_miptree_copy_teximage(struct brw_context

*brw,

Post by Jason Ekstrand
* functions on a miptree without HiZ. In that case, each function is a

no-op.

Post by Jason Ekstrand
*/
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Jason Ekstrand

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes.  One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
also enable CCS_E for window-system buffers which are Y-tiled.  They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
  src/mesa/drivers/dri/i965/brw_blorp.c         |   4 +-
  src/mesa/drivers/dri/i965/intel_fbo.c         |   2 +-
  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190

+++++++++++++-------------

Post by Jason Ekstrand
  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
  4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri

/i965/brw_blorp.c

Post by Jason Ekstrand
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct

gl_framebuffer *fb,

Post by Jason Ekstrand
     if (set_write_disables(irb, ctx->Color.ColorMask[buf],

color_write_disable))

Post by Jason Ekstrand
        can_fast_clear = false;
-   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+   if (!irb->mt->supports_fast_clear ||
         !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->

Color.ClearColor))

Post by Jason Ekstrand
        can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct

gl_framebuffer *fb,

Post by Jason Ekstrand
         */
        if (!irb->mt->mcs_buf) {
           assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
-         if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+         if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
              /* MCS allocation failed--probably this will only happen in
               * out-of-memory conditions.  But in any case, try to

recover

Post by Jason Ekstrand
               * by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri

/i965/intel_fbo.c

Post by Jason Ekstrand
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context

*brw,

Post by Jason Ekstrand
     intel_renderbuffer_set_draw_offset(irb);
-   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
        intel_miptree_alloc_hiz(brw, mt);
        if (!mt->hiz_buf)
        return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/

drivers/dri/i965/intel_mipmap_tree.c

Post by Jason Ekstrand
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
   */
  static enum intel_msaa_layout
  compute_msaa_layout(struct brw_context *brw, mesa_format format,
-                    enum intel_aux_disable aux_disable)
+                    uint32_t layout_flags)
  {
     /* Prior to Gen7, all MSAA surfaces used IMS layout. */
     if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,

mesa_format format,

Post by Jason Ekstrand
         */
        if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT)

{

Post by Jason Ekstrand
           return INTEL_MSAA_LAYOUT_UMS;
-      } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+      } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
           /* We can't use the CMS layout because it uses an aux buffer,

the MCS

Post by Jason Ekstrand
            * buffer. So fallback to UMS, which is identical to CMS

without the

Post by Jason Ekstrand
            * MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
     if (brw->gen < 7)
        return false;
-   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
-      return false;
-
     /* This function applies only to non-multisampled render targets. */
     if (mt->num_samples > 1)
        return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
        return true;
  }
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+                           struct intel_mipmap_tree *mt)
+{
+   if (!brw->has_hiz)
+      return false;
+
+   switch (mt->format) {
+      return true;
+      return false;
+   }
+}
+
+
  /* On Gen9 support for color buffer compression was extended to single
   * sampled surfaces. This is a helper considering both auxiliary buffer
   * type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context *brw,
     mt->logical_width0 = width0;
     mt->logical_height0 = height0;
     mt->logical_depth0 = depth0;
-   mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
-      INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
-   mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
     mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+   mt->aux_usage = ISL_AUX_USAGE_NONE;
+   mt->supports_fast_clear = false;
     mt->aux_state = NULL;
     mt->cpp = _mesa_get_format_bytes(format);
     mt->num_samples = num_samples;
@@ -337,7 +353,7 @@ intel_miptree_create_layout(struct brw_context *brw,
     int depth_multiply = 1;
     if (num_samples > 1) {
        /* Adjust width/height/depth for MSAA */
-      mt->msaa_layout = compute_msaa_layout(brw, format, mt->

aux_disable);

Post by Jason Ekstrand
+      mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
        if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
            * "If the surface is multisampled and it is a depth or stencil
@@ -460,8 +476,7 @@ intel_miptree_create_layout(struct brw_context *brw,
     if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
         _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
         (brw->must_use_separate_stencil ||
-     (brw->has_separate_stencil &&
-         intel_miptree_wants_hiz_buffer(brw, mt)))) {
+     (brw->has_separate_stencil && intel_miptree_supports_hiz(brw,

mt)))) {

Post by Jason Ekstrand
        uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
        if (brw->gen == 6) {
           stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
@@ -530,14 +545,44 @@ intel_miptree_create_layout(struct brw_context

*brw,

Post by Jason Ekstrand
        return NULL;
     }
-   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
-      assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
     return mt;
  }
  /**
+ * Choose the aux usage for this miptree.  This function must be called

fairly

Post by Jason Ekstrand
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+                               struct intel_mipmap_tree *mt)
+{
+   assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+      mt->aux_usage = ISL_AUX_USAGE_MCS;
+   } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+              intel_miptree_supports_ccs(brw, mt)) {
+      if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+          brw->gen >= 9 && !mt->is_scanout &&
+          intel_miptree_supports_ccs_e(brw, mt)) {
+         mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+      } else {
+         mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+      }
+   } else if (intel_miptree_supports_hiz(brw, mt)) {
+      mt->aux_usage = ISL_AUX_USAGE_HIZ;
+   }
+
+   /* We can do fast-clear on all auxiliary surface types that are
+    * allocated through the normal texture creation paths.
+    */
+   if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+      mt->supports_fast_clear = true;
+}
+
+
+/**
   * Choose an appropriate uncompressed format for a requested
   * compressed format, if unsupported.
   */
@@ -670,6 +715,9 @@ miptree_create(struct brw_context *brw,
     if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
        mt->bo->cache_coherent = false;
+   if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+      intel_miptree_choose_aux_usage(brw, mt);
+
     return mt;
  }
@@ -726,29 +774,14 @@ intel_miptree_create(struct brw_context *brw,
        }
     }
-   /* If this miptree is capable of supporting fast color clears, set
-    * fast_clear_state appropriately to ensure that fast clears will

occur.

Post by Jason Ekstrand
-    * Allocation of the MCS miptree will be deferred until the first

fast

Post by Jason Ekstrand
-    * clear actually occurs or when compressed single sampled buffer is
-    * written by the GPU for the first time.
+   /* Since CCS_E can compress more than just clear color, we create the

CCS

Post by Jason Ekstrand
+    * for it up-front.  For CCS_D which only compresses clears, we

create the

Post by Jason Ekstrand
+    * CCS on-demand when a clear occurs that wants one.
      */

The above comment...

Post by Jason Ekstrand
-   if (intel_tiling_supports_ccs(brw, mt->tiling) &&
-       intel_miptree_supports_ccs(brw, mt)) {
-      mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
-      assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
-      /* On Gen9+ clients are not currently capable of consuming

compressed

Post by Jason Ekstrand
-       * single-sampled buffers. Disabling compression allows us to skip
-       * resolves.
-       */
-      const bool lossless_compression_disabled = INTEL_DEBUG &

DEBUG_NO_RBC;

Post by Jason Ekstrand
-      const bool is_lossless_compressed =
-         unlikely(!lossless_compression_disabled) &&
-         brw->gen >= 9 && !mt->is_scanout &&
-         intel_miptree_supports_ccs_e(brw, mt);
-
-      if (is_lossless_compressed) {
-         intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+   if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+      if (!intel_miptree_alloc_ccs(brw, mt)) {
+         intel_miptree_release(&mt);
+         return NULL;
        }

...and the above hunk appear twice in the commit. I believe that both
locations are necessary and sufficient. However, you can replace them
with a single location.
Also, the patch contains two calls to intel_miptree_choose_aux_usage().
Again, you can replace them with a single call.
Intstead of having these two things duplicated, I think they should
intel_miptree_create_layout(). That should lead to less fragile code,
I hope.
    * All miptree creation paths eventually lead to
      intel_miptree_create_layout().
    * The result of intel_miptree_choose_aux_usage() depends directly on
      mt->msaa_layout and indirectly on mt->tiling. As far as I can
      tell, it depends on no other miptree state.
    * mt->msaa_layout is set in exactly two places: the top of
      intel_miptree_create_layout() and as a side-effect of
      intel_miptree_alloc_ccs(). (Why intel_miptree_alloc_ccs, formerly
      intel_miptree_alloc_non_msrt_mcs, sets mt->msaa_layout to
      INTEL_MSAA_LAYOUT_CMS is a mystery to me. I choose to ignore it,
      because I suspect that assignment is nowhere used afterwards.
      WARNING: I have left the realm of facts!)
        a. intel_miptree_create_layout() sometimes sets mt->tiling as one
of its
           last actions, when it calls brw_miptree_layout(). "sometimes",
           because brw_miptree_layout() sets mt->tiling if and only if
           !MIPTREE_LAYOUT_FOR_BO.
        b. intel_miptree_create_for_bo() sets mt->tiling immediately
           after calling intel_miptree_create_layout().
        c. miptree_create() sets mt->tiling in a weird fallback
           immediately after it calls intel_miptree_create_layout().
    * You can collapse the two calls of
      intel_miptree_choose_aux_usage(), and the two pre-allocations of
      the ccs_e, into a single location (which I'll call "pot o' gold")
      at the tail of intel_miptree_create_layout() immediately before it
      returns, IF...
        * IF the pot o' gold happens after mt->msaa_layout is set. This
          is trivial because mt->msaa_layout is set at the top of
          intel_miptree_create_layout() and nowhere else, modulo my
          willfull ignorance of intel_miptree_alloc_ccs's weirdness.
        * IF the pot o' gold happens after mt->tiling is set. What's
          * Move the mt->tiling assignment in (b)
            to occur immediately before the call to
intel_miptree_create_layout().
            Trivial fixup.
          * Fix the weird tiling fallback in item (c) by pushing it into
            intel_miptree_create_layout(). Another trivial fixup.
I expect that I missed some details. I await your rebuttal.
You are correct that they could be placed on the common path, sort of.  You are
wrong that it's a good idea.  Why?  Modifiers.  With modifiers, we have to
override the choice of aux and create the auxiliary surface ourselves so we
don't want it created for us.  But we also can't create it with DISABLE_AUX
because we may want it to still do HALIGN16 if we're going to create one
ourselves.  So, instead, what we do is to let create_for_bo go ahead and choose
aux usage, then we stomp it to what we want, and then we set up the CCS.  We
could choose aux usage in create_layout but I figured that would hint that aux
usage was something entirely chose by create_layout and not stompped later.  I
don't like to imply that.

I fast-forwarded through the patch series, and see the final result in
intel_miptree_create_for_dri_image(). Now I see why you want to make
last-minute aux decisions for intel_miptree_create_for_dri_image() but
not intel_miptree_create().

That was only issue with the patch. So,
Reviewed-by: Chad Versace <***@chromium.org>

[Chad Versace]

Post by Jason Ekstrand
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.
This commit makes functional changes. One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. It should
also enable CCS_E for window-system buffers which are Y-tiled. They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 +++++++++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 43 +++---
4 files changed, 120 insertions(+), 119 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
can_fast_clear = false;
- if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+ if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
can_fast_clear = false;
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (!irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {

The above assert is useless post-patch, because it occurs inside if
(!irb->mt->mcs_buf) and the top of intel_miptree_is_lossless_compressed
looks like this:

/* first check */
if (brw->gen < 9)
return false;

/* second check */
if (!mt->mcs_buf)
return false;

...

Just an observation.

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.

v2: Make the return type a bool (Topi)

v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Signed-off-by: Ben Widawsky <***@intel.com>
Acked-by: Daniel Stone <***@collabora.com>
Reviewed-by: Topi Pohjolainen <***@intel.com> (v2)
---
src/mesa/drivers/dri/i965/brw_context.c | 16 ++++++++++------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 5433f90..e963e13 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1611,9 +1611,12 @@ intel_process_dri2_buffer(struct brw_context *brw,
return;
}

- intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
- drawable->w, drawable->h,
- buffer->pitch);
+ if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ drawable->w, drawable->h,
+ buffer->pitch)) {
+ brw_bo_unreference(bo);
+ return;
+ }

if (_mesa_is_front_buffer_drawing(fb) &&
(buffer->attachment == __DRI_BUFFER_FRONT_LEFT ||
@@ -1669,9 +1672,10 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
return;

- intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
- buffer->width, buffer->height,
- buffer->pitch);
+ if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ buffer->width, buffer->height,
+ buffer->pitch))
+ return;

if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6e94ba3..893f13e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -957,7 +957,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
* that will contain the actual rendering (which is lazily resolved to
* irb->singlesample_mt).
*/
-void
+bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
struct brw_bo *bo,
@@ -1013,12 +1013,12 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
irb->mt = multisample_mt;
}
}
- return;
+ return true;

fail:
intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
- return;
+ return false;
}

struct intel_mipmap_tree*
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 9b6bc40..04aab2d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -701,7 +701,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target);

-void
+bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
struct brw_bo *bo,

[Pohjolainen, Topi]

Post by Jason Ekstrand
There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.
v2: Make the return type a bool (Topi)
v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Version 3 also.

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_context.c | 16 ++++++++++------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 5433f90..e963e13 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1611,9 +1611,12 @@ intel_process_dri2_buffer(struct brw_context *brw,
return;
}
- intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
- drawable->w, drawable->h,
- buffer->pitch);
+ if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ drawable->w, drawable->h,
+ buffer->pitch)) {
+ brw_bo_unreference(bo);
+ return;
+ }
if (_mesa_is_front_buffer_drawing(fb) &&
(buffer->attachment == __DRI_BUFFER_FRONT_LEFT ||
@@ -1669,9 +1672,10 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
return;
- intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
- buffer->width, buffer->height,
- buffer->pitch);
+ if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ buffer->width, buffer->height,
+ buffer->pitch))
+ return;
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6e94ba3..893f13e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -957,7 +957,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
* that will contain the actual rendering (which is lazily resolved to
* irb->singlesample_mt).
*/
-void
+bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
struct brw_bo *bo,
@@ -1013,12 +1013,12 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
irb->mt = multisample_mt;
}
}
- return;
+ return true;
intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
- return;
+ return false;
}
struct intel_mipmap_tree*
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 9b6bc40..04aab2d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -701,7 +701,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target);
-void
+bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
struct brw_bo *bo,
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Jason Ekstrand
There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.
v2: Make the return type a bool (Topi)
v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/brw_context.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index f57045f..9a55e44 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1689,15 +1689,8 @@ intel_update_image_buffer(struct brw_context *intel,
return;

struct intel_mipmap_tree *mt =
- intel_miptree_create_for_bo(intel,
- buffer->bo,
- intel_rb_format(rb),
- 0,
- buffer->width,
- buffer->height,
- 1,
- buffer->pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
+ intel_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D,
+ intel_rb_format(rb), true);
if (!mt)
return;

[Chad Versace]

Patches 14 and 15 are
Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

This is a bit ugly, but I think it's the best one can do.

v2: This patch let's us remove the temporary no_aux variable since mt
allocation should work correctly now.
Unref the BO is miptree creation fails (Jason)
v3: Rebase (Daniel)

Cc: Jason Ekstrand <***@jlekstrand.net>
Signed-off-by: Ben Widawsky <***@bwidawsk.net>
Acked-by: Daniel Stone <***@collabora.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 37 ++++++++++++++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++----------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 37 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e963e13..f57045f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1611,10 +1611,26 @@ intel_process_dri2_buffer(struct brw_context *brw,
return;
}

- if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw,
+ bo,
+ intel_rb_format(rb),
+ 0,
+ drawable->w,
+ drawable->h,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt) {
+ brw_bo_unreference(bo);
+ return;
+ }
+
+ if (!intel_update_winsys_renderbuffer_miptree(brw, rb, mt,
drawable->w, drawable->h,
buffer->pitch)) {
brw_bo_unreference(bo);
+ intel_miptree_release(&mt);
return;
}

@@ -1672,10 +1688,25 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
return;

- if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(intel,
+ buffer->bo,
+ intel_rb_format(rb),
+ 0,
+ buffer->width,
+ buffer->height,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt)
+ return;
+
+ if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
buffer->width, buffer->height,
- buffer->pitch))
+ buffer->pitch)) {
+ intel_miptree_release(&mt);
return;
+ }

if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 893f13e..08c13fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -960,11 +960,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch)
{
- struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
@@ -976,17 +975,7 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
assert(_mesa_get_format_base_format(format) == GL_RGB ||
_mesa_get_format_base_format(format) == GL_RGBA);

- singlesample_mt = intel_miptree_create_for_bo(intel,
- bo,
- format,
- 0,
- width,
- height,
- 1,
- pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
- if (!singlesample_mt)
- goto fail;
+ assert(singlesample_mt);

if (num_samples == 0) {
intel_miptree_release(&irb->mt);
@@ -1016,7 +1005,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
return true;

fail:
- intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
return false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 04aab2d..7b702a3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -704,7 +704,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch);

[Pohjolainen, Topi]

Post by Jason Ekstrand
Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

Just looking this patch locally I don't really understand this commit
message. I'll keep on reading if the answer is later in the series..

Post by Jason Ekstrand
This is a bit ugly, but I think it's the best one can do.
v2: This patch let's us remove the temporary no_aux variable since mt
allocation should work correctly now.
Unref the BO is miptree creation fails (Jason)
v3: Rebase (Daniel)
---
src/mesa/drivers/dri/i965/brw_context.c | 37 ++++++++++++++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++----------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e963e13..f57045f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1611,10 +1611,26 @@ intel_process_dri2_buffer(struct brw_context *brw,
return;
}
- if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw,
+ bo,
+ intel_rb_format(rb),
+ 0,
+ drawable->w,
+ drawable->h,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt) {
+ brw_bo_unreference(bo);
+ return;
+ }
+
+ if (!intel_update_winsys_renderbuffer_miptree(brw, rb, mt,
drawable->w, drawable->h,
buffer->pitch)) {
brw_bo_unreference(bo);
+ intel_miptree_release(&mt);
return;
}
@@ -1672,10 +1688,25 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
return;
- if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(intel,
+ buffer->bo,
+ intel_rb_format(rb),
+ 0,
+ buffer->width,
+ buffer->height,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt)
+ return;
+
+ if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
buffer->width, buffer->height,
- buffer->pitch))
+ buffer->pitch)) {
+ intel_miptree_release(&mt);
return;
+ }
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 893f13e..08c13fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -960,11 +960,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch)
{
- struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
@@ -976,17 +975,7 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
assert(_mesa_get_format_base_format(format) == GL_RGB ||
_mesa_get_format_base_format(format) == GL_RGBA);
- singlesample_mt = intel_miptree_create_for_bo(intel,
- bo,
- format,
- 0,
- width,
- height,
- 1,
- pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
- if (!singlesample_mt)
- goto fail;
+ assert(singlesample_mt);
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
@@ -1016,7 +1005,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
return true;
- intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
return false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 04aab2d..7b702a3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -704,7 +704,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch);
--
2.5.0.400.gff86faf
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Pohjolainen, Topi]

Post by Pohjolainen, Topi

Post by Jason Ekstrand
Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

Just looking this patch locally I don't really understand this commit
message. I'll keep on reading if the answer is later in the series..

Looking the rest of the series the message given here is still confusing.
Something of this sort I would understand:

Later patches require intel_update_image_buffer() to have control over the
miptree creation. Currently, however, intel_update_winsys_renderbuffer_miptree()
creates it based on the given buffer object. This patch moves the creation to
the caller side.

Post by Pohjolainen, Topi

Post by Jason Ekstrand
This is a bit ugly, but I think it's the best one can do.
v2: This patch let's us remove the temporary no_aux variable since mt
allocation should work correctly now.
Unref the BO is miptree creation fails (Jason)
v3: Rebase (Daniel)
---
src/mesa/drivers/dri/i965/brw_context.c | 37 ++++++++++++++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++----------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e963e13..f57045f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1611,10 +1611,26 @@ intel_process_dri2_buffer(struct brw_context *brw,
return;
}
- if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw,
+ bo,
+ intel_rb_format(rb),
+ 0,
+ drawable->w,
+ drawable->h,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt) {
+ brw_bo_unreference(bo);
+ return;
+ }
+
+ if (!intel_update_winsys_renderbuffer_miptree(brw, rb, mt,
drawable->w, drawable->h,
buffer->pitch)) {
brw_bo_unreference(bo);
+ intel_miptree_release(&mt);
return;
}
@@ -1672,10 +1688,25 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
return;
- if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(intel,
+ buffer->bo,
+ intel_rb_format(rb),
+ 0,
+ buffer->width,
+ buffer->height,
+ 1,
+ buffer->pitch,
+ MIPTREE_LAYOUT_FOR_SCANOUT);
+ if (!mt)
+ return;
+
+ if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
buffer->width, buffer->height,
- buffer->pitch))
+ buffer->pitch)) {
+ intel_miptree_release(&mt);
return;
+ }
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 893f13e..08c13fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -960,11 +960,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch)
{
- struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
@@ -976,17 +975,7 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
assert(_mesa_get_format_base_format(format) == GL_RGB ||
_mesa_get_format_base_format(format) == GL_RGBA);
- singlesample_mt = intel_miptree_create_for_bo(intel,
- bo,
- format,
- 0,
- width,
- height,
- 1,
- pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
- if (!singlesample_mt)
- goto fail;
+ assert(singlesample_mt);
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
@@ -1016,7 +1005,6 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
return true;
- intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
return false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 04aab2d..7b702a3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -704,7 +704,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch);
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Chad Versace]

Post by Pohjolainen, Topi

Post by Jason Ekstrand
Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

Just looking this patch locally I don't really understand this commit
message. I'll keep on reading if the answer is later in the series..

I second Topi. I don't understand the commit message.

The code itself looks good, though.

[Jason Ekstrand]

Post by Jason Ekstrand

Post by Pohjolainen, Topi

Post by Jason Ekstrand
Allows us to continue utilizing common miptree creation using

__DRIimage

Post by Pohjolainen, Topi

Post by Jason Ekstrand
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

Just looking this patch locally I don't really understand this commit
message. I'll keep on reading if the answer is later in the series..

I second Topi. I don't understand the commit message.

I took a very slightly modified version of what topi wrote.

Post by Jason Ekstrand
The code itself looks good, though.

[Chad Versace]

Post by Jason Ekstrand

Post by Pohjolainen, Topi

Post by Jason Ekstrand
Allows us to continue utilizing common miptree creation using

__DRIimage

Post by Pohjolainen, Topi

Post by Jason Ekstrand
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

Just looking this patch locally I don't really understand this commit
message. I'll keep on reading if the answer is later in the series..

I second Topi. I don't understand the commit message.
I took a very slightly modified version of what topi wrote.

Then this patch is
Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/intel/isl/isl.h | 3 +++
src/intel/isl/isl_drm.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index eb05b54..dc3eada 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1513,6 +1513,9 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
}

+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling);
+
const struct isl_drm_modifier_info * ATTRIBUTE_CONST
isl_drm_modifier_get_info(uint64_t modofier);

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 8fccc40..1dc3da2 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -25,10 +25,33 @@
#include <stdlib.h>

#include <drm_fourcc.h>
+#include <i915_drm.h>

#include "isl.h"
#include "common/gen_device_info.h"

+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling)
+{
+ switch (tiling) {
+ case ISL_TILING_LINEAR:
+ return I915_TILING_NONE;
+
+ case ISL_TILING_X:
+ return I915_TILING_X;
+
+ case ISL_TILING_Y0:
+ return I915_TILING_Y;
+
+ case ISL_TILING_W:
+ case ISL_TILING_Yf:
+ case ISL_TILING_Ys:
+ case ISL_TILING_HIZ:
+ case ISL_TILING_CCS:
+ return I915_TILING_NONE;
+ }
+}
+
struct isl_drm_modifier_info modifier_info[] = {
{
.modifier = DRM_FORMAT_MOD_NONE,

[Pohjolainen, Topi]

In the subject: s/fro/from/

Post by Jason Ekstrand
---
src/intel/isl/isl.h | 3 +++
src/intel/isl/isl_drm.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index eb05b54..dc3eada 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1513,6 +1513,9 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
}
+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling);
+
const struct isl_drm_modifier_info * ATTRIBUTE_CONST
isl_drm_modifier_get_info(uint64_t modofier);
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 8fccc40..1dc3da2 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -25,10 +25,33 @@
#include <stdlib.h>
#include <drm_fourcc.h>
+#include <i915_drm.h>
#include "isl.h"
#include "common/gen_device_info.h"
+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling)
+{
+ switch (tiling) {
+ return I915_TILING_NONE;
+
+ return I915_TILING_X;
+
+ return I915_TILING_Y;
+
+ return I915_TILING_NONE;
+ }
+}
+
struct isl_drm_modifier_info modifier_info[] = {
{
.modifier = DRM_FORMAT_MOD_NONE,
--
2.5.0.400.gff86faf
_______________________________________________
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[Chad Versace]

Post by Jason Ekstrand
---
src/intel/isl/isl.h | 3 +++
src/intel/isl/isl_drm.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
src/mesa/drivers/dri/i965/intel_screen.h | 4 ++++
3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 9a55e44..15d66ee 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -960,7 +960,7 @@ brwCreateContext(gl_api api,
brw->must_use_separate_stencil = devinfo->must_use_separate_stencil;
brw->has_swizzling = screen->hw_has_swizzling;

- isl_device_init(&brw->isl_dev, devinfo, screen->hw_has_swizzling);
+ brw->isl_dev = screen->isl_dev;

brw->vs.base.stage = MESA_SHADER_VERTEX;
brw->tcs.base.stage = MESA_SHADER_TESS_CTRL;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 83b8a24..3cf10b8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2095,6 +2095,9 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->hw_has_swizzling = intel_detect_swizzling(screen);
screen->hw_has_timestamp = intel_detect_timestamp(screen);

+ isl_device_init(&screen->isl_dev, &screen->devinfo,
+ screen->hw_has_swizzling);
+
/* GENs prior to 8 do not support EU/Subslice info */
if (devinfo->gen >= 8) {
intel_detect_sseu(screen);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index f9c1db6..ce93ae0 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -37,6 +37,8 @@
#include "i915_drm.h"
#include "xmlconfig.h"

+#include "isl/isl.h"
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -59,6 +61,8 @@ struct intel_screen

int hw_has_timestamp;

+ struct isl_device isl_dev;
+
/**
* Does the kernel support context reset notifications?
*/

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
src/mesa/drivers/dri/i965/intel_screen.h | 4 ++++
3 files changed, 8 insertions(+), 1 deletion(-)

Patch 17 is
Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

Any form of CCS on gen9+ only works on Y-tiled images. The only caller
of create_for_bo which uses Y-tiled BOs is create_for_dri_image.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 83c99ed..e3de386 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -839,21 +839,9 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->offset = offset;
mt->tiling = tiling;

- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
intel_miptree_choose_aux_usage(brw, mt);

- /* Since CCS_E can compress more than just clear color, we create the
- * CCS for it up-front. For CCS_D which only compresses clears, we
- * create the CCS on-demand when a clear occurs that wants one.
- */
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- if (!intel_miptree_alloc_ccs(brw, mt)) {
- intel_miptree_release(&mt);
- return NULL;
- }
- }
- }
-
return mt;
}

@@ -955,6 +943,17 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}

+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
return mt;
}

[Chad Versace]

Post by Jason Ekstrand
Any form of CCS on gen9+ only works on Y-tiled images. The only caller
of create_for_bo which uses Y-tiled BOs is create_for_dri_image.

If I understand ARC++ correctly, then intel_update_image_buffer() also
calls intel_miptree_create_for_bo() for Android Y-tiled winsys buffers.
(I've confirmed it with code inspection, but not with actual debug
logging). That should be noted in the commit message.

This patch shouldn't degrade ARC++ performance, though, because ARC++ is
still using an old Mesa that never allocated CCS for Android winsys
buffers.

At the end of the patch series, will Android's Y-tiled winsys buffers
get the benefit of a private CCS?

Post by Jason Ekstrand
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+

The above hunk is a duplicate. The same 'if' tree appears immediately
above it.

With the hunk de-duplicated, this patch is

Post by Jason Ekstrand
return mt;
}
--
2.5.0.400.gff86faf
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

Post by Chad Versace

Post by Jason Ekstrand
Any form of CCS on gen9+ only works on Y-tiled images. The only caller
of create_for_bo which uses Y-tiled BOs is create_for_dri_image.

If I understand ARC++ correctly, then intel_update_image_buffer() also
calls intel_miptree_create_for_bo() for Android Y-tiled winsys buffers.
(I've confirmed it with code inspection, but not with actual debug
logging). That should be noted in the commit message.
This patch shouldn't degrade ARC++ performance, though, because ARC++ is
still using an old Mesa that never allocated CCS for Android winsys
buffers.

No, it shouldn't degrade ARC++ performance because patch 15 (the previous
one) makes intel_update_image_buffer() call
intel_miptree_create_for_dri_image(). :-)

--Jason

Post by Chad Versace
At the end of the patch series, will Android's Y-tiled winsys buffers
get the benefit of a private CCS?

Post by Jason Ekstrand
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+

The above hunk is a duplicate. The same 'if' tree appears immediately
above it.

It wasn't duplicated so much as rebased into the wrong hunk. It should
have ended up in create_for_dri_image. I've moved it.

Post by Chad Versace
With the hunk de-duplicated, this patch is

Thanks!

Post by Chad Versace

Post by Jason Ekstrand
return mt;
}
--
2.5.0.400.gff86faf
_______________________________________________
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[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_fbo.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 6a64bcb..f1a997b 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,31 +362,10 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
* buffer's content to the main buffer nor for invalidating the aux buffer's
* content.
*/
- irb->mt = intel_miptree_create_for_bo(brw,
- image->bo,
- image->format,
- image->offset,
- image->width,
- image->height,
- 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+ irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D);
if (!irb->mt)
return;

- /* Adjust the miptree's upper-left coordinate.
- *
- * FIXME: Adjusting the miptree's layout outside of
- * intel_miptree_create_layout() is fragile. Plumb the adjustment through
- * intel_miptree_create_layout() and brw_tex_layout().
- */
- irb->mt->level[0].level_x = image->tile_x;
- irb->mt->level[0].level_y = image->tile_y;
- irb->mt->level[0].slice[0].x_offset = image->tile_x;
- irb->mt->level[0].slice[0].y_offset = image->tile_y;
- irb->mt->total_width += image->tile_x;
- irb->mt->total_height += image->tile_y;
-
rb->InternalFormat = image->internal_format;
rb->Width = image->width;
rb->Height = image->height;

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_fbo.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)

Please note in the commit message that this does introduce a functional
change. intel_image_target_renderbuffer_storage() now fails if
!brw->format_supported_as_render_target || !ctx->TextureFormatSupported,
while before it only checked !brw->format_supported_as_render_target.

I believe that ctx->TextureFormatSupported is a superset of
brw->format_supported_as_render_target, so this shouldn't cause any
problems. But it's nice to record in the git log just in case a bug
bisects to here.

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.h | 22 +++++++++++++++++
src/intel/isl/isl_drm.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 83 insertions(+)
create mode 100644 src/intel/isl/isl_drm.c

diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am
index 269d73d..02c625a 100644
--- a/src/intel/Makefile.am
+++ b/src/intel/Makefile.am
@@ -38,6 +38,7 @@ AM_CPPFLAGS = \
-I$(top_srcdir)/src/gallium/auxiliary \
-I$(top_srcdir)/src/gallium/include \
$(VALGRIND_CFLAGS) \
+ $(LIBDRM_CFLAGS) \
$(DEFINES)

AM_CFLAGS = \
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index a877ff2..01ace0b 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -147,6 +147,7 @@ GENXML_GENERATED_FILES = \
ISL_FILES = \
isl/isl.c \
isl/isl.h \
+ isl/isl_drm.c \
isl/isl_format.c \
isl/isl_priv.h \
isl/isl_storage_image.c
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 95ecaf9..eb05b54 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1032,6 +1032,25 @@ struct isl_tile_info {
};

/**
+ * Metadata about a DRM format modifier.
+ */
+struct isl_drm_modifier_info {
+ uint64_t modifier;
+
+ /** Text name of the modifier */
+ const char *name;
+
+ /** ISL tiling implied by this modifier */
+ enum isl_tiling tiling;
+
+ /** ISL aux usage implied by this modifier */
+ enum isl_aux_usage aux_usage;
+
+ /** Whether or not this modifier supports clear color */
+ bool supports_clear_color;
+};
+
+/**
* @brief Input to surface initialization
*
* @invariant width >= 1
@@ -1494,6 +1513,9 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
}

+const struct isl_drm_modifier_info * ATTRIBUTE_CONST
+isl_drm_modifier_get_info(uint64_t modofier);
+
struct isl_extent2d ATTRIBUTE_CONST
isl_get_interleaved_msaa_px_size_sa(uint32_t samples);

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
new file mode 100644
index 0000000..8fccc40
--- /dev/null
+++ b/src/intel/isl/isl_drm.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include <drm_fourcc.h>
+
+#include "isl.h"
+#include "common/gen_device_info.h"
+
+struct isl_drm_modifier_info modifier_info[] = {
+ {
+ .modifier = DRM_FORMAT_MOD_NONE,
+ .name = "DRM_FORMAT_MOD_NONE",
+ .tiling = ISL_TILING_LINEAR,
+ },
+ {
+ .modifier = I915_FORMAT_MOD_X_TILED,
+ .name = "I915_FORMAT_MOD_X_TILED",
+ .tiling = ISL_TILING_X,
+ },
+ {
+ .modifier = I915_FORMAT_MOD_Y_TILED,
+ .name = "I915_FORMAT_MOD_Y_TILED",
+ .tiling = ISL_TILING_Y0,
+ },
+};
+
+const struct isl_drm_modifier_info *
+isl_drm_modifier_get_info(uint64_t modifier)
+{
+ for (unsigned i = 0; i < ARRAY_SIZE(modifier_info); i++) {
+ if (modifier_info[i].modifier == modifier)
+ return &modifier_info[i];
+ }
+
+ return NULL;
+}

[Chad Versace]

Post by Jason Ekstrand
---
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.h | 22 +++++++++++++++++
src/intel/isl/isl_drm.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 83 insertions(+)
create mode 100644 src/intel/isl/isl_drm.c
+const struct isl_drm_modifier_info * ATTRIBUTE_CONST
+isl_drm_modifier_get_info(uint64_t modofier);

Typo in 'modoifier'.

Other than that, this patch is
Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

We want to start using create_for_dri_image for all miptrees created
from __DRIimage, including those which come from a window system. In
order to allow for fast clears to still work on window system buffers,
we need to allow for creating aux surfaces.
---
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
4 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 130eab1..db4cfee 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -363,7 +363,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
* content.
*/
irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
- image->format);
+ image->format, false);
if (!irb->mt)
return;

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b4d431..83c99ed 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -901,7 +901,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
- mesa_format format)
+ mesa_format format,
+ bool is_winsys_image)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
@@ -909,6 +910,16 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
if (!brw->ctx.TextureFormatSupported[format])
return NULL;

+ /* If this image comes in from a window system, we have different
+ * requirements than if it comes in via an EGL import operation. Window
+ * system images can use any form of auxiliary compression we wish because
+ * they get "flushed" before being handed off to the window system and we
+ * have the opportunity to do resolves. Window system buffers also may be
+ * used for scanout so we need to flag that appropriately.
+ */
+ const uint32_t mt_layout_flags =
+ is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;
+
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
* buffer's content to the main buffer nor for invalidating the aux buffer's
@@ -917,8 +928,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+ image->pitch, mt_layout_flags);
if (mt == NULL)
return NULL;

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8044a1b..2a4cda2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -700,7 +700,8 @@ struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
- mesa_format format);
+ mesa_format format,
+ bool is_winsys_image);

bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 76a6e13..53e1087 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -344,7 +344,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
}

mt = intel_miptree_create_for_dri_image(brw, image, target,
- image->format);
+ image->format, false);
if (mt == NULL)
return;

[Pohjolainen, Topi]

Post by Jason Ekstrand
We want to start using create_for_dri_image for all miptrees created
from __DRIimage, including those which come from a window system. In
order to allow for fast clears to still work on window system buffers,
we need to allow for creating aux surfaces.
---
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
4 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 130eab1..db4cfee 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -363,7 +363,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
* content.
*/
irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
- image->format);
+ image->format, false);
if (!irb->mt)
return;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b4d431..83c99ed 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -901,7 +901,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
- mesa_format format)
+ mesa_format format,
+ bool is_winsys_image)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
@@ -909,6 +910,16 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
if (!brw->ctx.TextureFormatSupported[format])
return NULL;
+ /* If this image comes in from a window system, we have different
+ * requirements than if it comes in via an EGL import operation. Window
+ * system images can use any form of auxiliary compression we wish because
+ * they get "flushed" before being handed off to the window system and we
+ * have the opportunity to do resolves. Window system buffers also may be
+ * used for scanout so we need to flag that appropriately.
+ */
+ const uint32_t mt_layout_flags =
+ is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;

Is there any particular why we couldn't pass 'layout_flags' directly instead
of 'is_winsys_image'? That would work at least for the next patch in the
series.

Post by Jason Ekstrand
+
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
* buffer's content to the main buffer nor for invalidating the aux buffer's
@@ -917,8 +928,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+ image->pitch, mt_layout_flags);
if (mt == NULL)
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8044a1b..2a4cda2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -700,7 +700,8 @@ struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
- mesa_format format);
+ mesa_format format,
+ bool is_winsys_image);
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 76a6e13..53e1087 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -344,7 +344,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
}
mt = intel_miptree_create_for_dri_image(brw, image, target,
- image->format);
+ image->format, false);
if (mt == NULL)
return;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Pohjolainen, Topi]

Post by Pohjolainen, Topi

Post by Jason Ekstrand
We want to start using create_for_dri_image for all miptrees created
from __DRIimage, including those which come from a window system. In
order to allow for fast clears to still work on window system buffers,
we need to allow for creating aux surfaces.
---
src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
4 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 130eab1..db4cfee 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -363,7 +363,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
* content.
*/
irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
- image->format);
+ image->format, false);
if (!irb->mt)
return;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b4d431..83c99ed 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -901,7 +901,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
- mesa_format format)
+ mesa_format format,
+ bool is_winsys_image)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
@@ -909,6 +910,16 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
if (!brw->ctx.TextureFormatSupported[format])
return NULL;
+ /* If this image comes in from a window system, we have different
+ * requirements than if it comes in via an EGL import operation. Window
+ * system images can use any form of auxiliary compression we wish because
+ * they get "flushed" before being handed off to the window system and we
+ * have the opportunity to do resolves. Window system buffers also may be
+ * used for scanout so we need to flag that appropriately.
+ */
+ const uint32_t mt_layout_flags =
+ is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;

Is there any particular why we couldn't pass 'layout_flags' directly instead
of 'is_winsys_image'? That would work at least for the next patch in the
series.

Okay, I just read patch 25. Ignore this comment.

Post by Pohjolainen, Topi

Post by Jason Ekstrand
+
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
* buffer's content to the main buffer nor for invalidating the aux buffer's
@@ -917,8 +928,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+ image->pitch, mt_layout_flags);
if (mt == NULL)
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8044a1b..2a4cda2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -700,7 +700,8 @@ struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
- mesa_format format);
+ mesa_format format,
+ bool is_winsys_image);
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 76a6e13..53e1087 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -344,7 +344,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
}
mt = intel_miptree_create_for_dri_image(brw, image, target,
- image->format);
+ image->format, false);
if (mt == NULL)
return;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index f1a997b..130eab1 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,7 +362,8 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
* buffer's content to the main buffer nor for invalidating the aux buffer's
* content.
*/
- irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D);
+ irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
+ image->format);
if (!irb->mt)
return;

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 08c13fc..7b4d431 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -900,12 +900,13 @@ miptree_create_for_planar_image(struct brw_context *brw,

struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
- __DRIimage *image, GLenum target)
+ __DRIimage *image, GLenum target,
+ mesa_format format)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);

- if (!brw->ctx.TextureFormatSupported[image->format])
+ if (!brw->ctx.TextureFormatSupported[format])
return NULL;

/* Disable creation of the texture's aux buffers because the driver exposes
@@ -914,7 +915,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
* content.
*/
struct intel_mipmap_tree *mt =
- intel_miptree_create_for_bo(brw, image->bo, image->format,
+ intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
image->pitch,
MIPTREE_LAYOUT_DISABLE_AUX);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7b702a3..8044a1b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -699,7 +699,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
- GLenum target);
+ GLenum target,
+ mesa_format format);

bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 580e3b2..76a6e13 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -343,7 +343,8 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
return;
}

- mt = intel_miptree_create_for_dri_image(brw, image, target);
+ mt = intel_miptree_create_for_dri_image(brw, image, target,
+ image->format);
if (mt == NULL)
return;

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)

I dislike this patch. A lot.

The __DRIimage already has a 'format' member. Why is it necessary to
override that format? More importantly, *when* is it necessary?

In patch "i965: Use create_for_dri_image in intel_update_image_buffer",
I see that you pass intel_rb_format(rb) down as the 'format' parameter.
Is that the only place the override is needed? In that function, why do
the image's format and the renderbuffer's format differ? When do they
differ? When they do differ, is it illegal then to update the
image's format to match? If we don't update the image's format in
intel_update_image_buffer(), then does the invalidity of
__DRIimage::format cause potential issues elsewhere?

[...]

Post by Jason Ekstrand
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 08c13fc..7b4d431 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -900,12 +900,13 @@ miptree_create_for_planar_image(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
- __DRIimage *image, GLenum target)
+ __DRIimage *image, GLenum target,
+ mesa_format format)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
- if (!brw->ctx.TextureFormatSupported[image->format])
+ if (!brw->ctx.TextureFormatSupported[format])
return NULL;

The 'format' parameter is ignored if the image has a planar format. That
makes me suspicious. At a minimum, this needs

assert(!format == !image->planar_format)

or an explanation of why the assertion is invalid.

[Jason Ekstrand]

Post by Chad Versace

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)

I dislike this patch. A lot.
The __DRIimage already has a 'format' member. Why is it necessary to
override that format? More importantly, *when* is it necessary?
In patch "i965: Use create_for_dri_image in intel_update_image_buffer",
I see that you pass intel_rb_format(rb) down as the 'format' parameter.
Is that the only place the override is needed? In that function, why do
the image's format and the renderbuffer's format differ? When do they
differ? When they do differ, is it illegal then to update the
image's format to match? If we don't update the image's format in
intel_update_image_buffer(), then does the invalidity of
__DRIimage::format cause potential issues elsewhere?

I understand your concern.

Short answer to all of the above: sRGB.

The long answer is that the DRI formats do not specify a colorspace. (To
be fair, they don't need to because all window system buffers are sRGB).
Depending on the selected visual, the renderbuffer format may be sRGB or
not. In order for other i965 internals to work sanely, we need the miptree
format to match the renderbuffer format. We need to somehow copy the
sRGBness.

Would you feel more comfortable with a boolean sRGB parameter? That would
make the answers to the above questions much more obvious at the cost of
some code.

Post by Chad Versace
[...]

Post by Jason Ekstrand
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

Post by Jason Ekstrand
index 08c13fc..7b4d431 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -900,12 +900,13 @@ miptree_create_for_planar_image(struct

brw_context *brw,

Post by Jason Ekstrand
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
- __DRIimage *image, GLenum target)
+ __DRIimage *image, GLenum target,
+ mesa_format format)
{
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
- if (!brw->ctx.TextureFormatSupported[image->format])
+ if (!brw->ctx.TextureFormatSupported[format])
return NULL;

The 'format' parameter is ignored if the image has a planar format. That
makes me suspicious. At a minimum, this needs
assert(!format == !image->planar_format)
or an explanation of why the assertion is invalid.

I think if we do what I suggested above, this will become obvious.

[Daniel Stone]

Hi,

Post by Jason Ekstrand

Post by Chad Versace
In patch "i965: Use create_for_dri_image in intel_update_image_buffer",
I see that you pass intel_rb_format(rb) down as the 'format' parameter.
Is that the only place the override is needed? In that function, why do
the image's format and the renderbuffer's format differ? When do they
differ? When they do differ, is it illegal then to update the
image's format to match? If we don't update the image's format in
intel_update_image_buffer(), then does the invalidity of
__DRIimage::format cause potential issues elsewhere?

I understand your concern.
Short answer to all of the above: sRGB.
The long answer is that the DRI formats do not specify a colorspace. (To be
fair, they don't need to because all window system buffers are sRGB).
Depending on the selected visual, the renderbuffer format may be sRGB or
not. In order for other i965 internals to work sanely, we need the miptree
format to match the renderbuffer format. We need to somehow copy the
sRGBness.
Would you feel more comfortable with a boolean sRGB parameter? That would
make the answers to the above questions much more obvious at the cost of
some code.

s/boolean/enum/ and you're on. As said before, the number of booleans
in this series already makes me sad, let alone adding more.

Cheers,
Daniel

[Chad Versace]

Post by Daniel Stone
Hi,

Post by Jason Ekstrand
Would you feel more comfortable with a boolean sRGB parameter? That would
make the answers to the above questions much more obvious at the cost of
some code.

s/boolean/enum/ and you're on. As said before, the number of booleans
in this series already makes me sad, let alone adding more.

Yes, please. Pass an enum, and this code will become understandable.

[Daniel Stone]

Hi,

Post by Jason Ekstrand
The long answer is that the DRI formats do not specify a colorspace.

Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
equivalent to the latter, bar the addition of a special and unique
SARGB8 token, i.e. ARGB8888 with the sRGB transfer function (and
presumably primaries?). The rest are presumed UNORM.

Cheers,
Daniel

[Jason Ekstrand]

Post by Jason Ekstrand
Hi,
The long answer is that the DRI formats do not specify a colorspace.
Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
equivalent to the latter, bar the addition of a special and unique
SARGB8 token, i.e. ARGB8888 with the sRGB transfer function (and
presumably primaries?). The rest are presumed UNORM.

Wha? What's the difference between SARGB8 and ARGB8888 then? My
understanding was that scanout basically treats everything as sRGB anyway.
Clearly, my sRGB knowledge is imperfect.

As for enums, sure, that can probably happen. GL and ISL both have enums
for colorspace that we could re-use.

--Jason

[Daniel Stone]

Hi,

Post by Jason Ekstrand

Post by Daniel Stone

Post by Jason Ekstrand
The long answer is that the DRI formats do not specify a colorspace.

Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
equivalent to the latter, bar the addition of a special and unique
SARGB8 token, i.e. ARGB8888 with the sRGB transfer function (and
presumably primaries?). The rest are presumed UNORM.

Wha? What's the difference between SARGB8 and ARGB8888 then? My
understanding was that scanout basically treats everything as sRGB anyway.
Clearly, my sRGB knowledge is imperfect.

GBM_FORMAT_ARGB8888 (aka DRI_IMAGE_FOURCC_ARGB8888), gets mapped to
DRI_IMAGE_FORMAT_ARGB8888, which gets mapped to
MESA_FORMAT_B8G8R8X8_UNORM (dri_util.c). Only
DRI_IMAGE_{FORMAT,FOURCC}_SARGB8 (no defined GBM token, but you can
pass it through the GBM API and it'll work sometimes) gets mapped to a
MESA_FORMAT_*_SRGB. So AFAICT, to get an sRGB scanout buffer from
Mesa/GBM, you'd need to allocate UNORM and do inverse-gamma in your
frag shader.

Wayland similarly never maps anything to sRGB.

X11 always imports EGLImages as UNORM, so blending would be broken in
a composited environment if we were actually allocating sRGB.

i965 tries pretty hard to allocate sRGB images in the pre-DRIImage,
DRI2 (as in the X11 protocol named 'DRI2') codepath, but this isn't
used by Wayland, GBM, or DRI3.

So no, not for pretty much any externally-visible images AFAICT. Even
if it were true for scanout, the client would need to tell KMS, so KMS
could send a HDMI infoframe telling the display.

Colourspaces \_o_/

Post by Jason Ekstrand
As for enums, sure, that can probably happen. GL and ISL both have enums
for colorspace that we could re-use.

Yes, having too few format tokens is not a problem we have. We seem to
have about as many of those as we have things called 'DRI2'.

Cheers,
Daniel

[Jason Ekstrand]

Post by Jason Ekstrand
Hi,

Post by Jason Ekstrand

Post by Daniel Stone

Post by Jason Ekstrand
The long answer is that the DRI formats do not specify a colorspace.

Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
equivalent to the latter, bar the addition of a special and unique
SARGB8 token, i.e. ARGB8888 with the sRGB transfer function (and
presumably primaries?). The rest are presumed UNORM.

Wha? What's the difference between SARGB8 and ARGB8888 then? My
understanding was that scanout basically treats everything as sRGB

anyway.

Post by Jason Ekstrand
Clearly, my sRGB knowledge is imperfect.

GBM_FORMAT_ARGB8888 (aka DRI_IMAGE_FOURCC_ARGB8888), gets mapped to
DRI_IMAGE_FORMAT_ARGB8888, which gets mapped to
MESA_FORMAT_B8G8R8X8_UNORM (dri_util.c). Only
DRI_IMAGE_{FORMAT,FOURCC}_SARGB8 (no defined GBM token, but you can
pass it through the GBM API and it'll work sometimes) gets mapped to a
MESA_FORMAT_*_SRGB. So AFAICT, to get an sRGB scanout buffer from
Mesa/GBM, you'd need to allocate UNORM and do inverse-gamma in your
frag shader.
Wayland similarly never maps anything to sRGB.
X11 always imports EGLImages as UNORM, so blending would be broken in
a composited environment if we were actually allocating sRGB.

Blending *is* broken. I had a long chat with Owen Taylor about this some
time ago. Everything comes into X11 sRGB encoded and scanout treats it's
buffer as sRGB. X11 then stomps everything to UNORM and blends in the
wrong colorspace.

Post by Jason Ekstrand
i965 tries pretty hard to allocate sRGB images in the pre-DRIImage,
DRI2 (as in the X11 protocol named 'DRI2') codepath, but this isn't
used by Wayland, GBM, or DRI3.

Except that whether you get an sRGB renderbuffer or not is governed by GLX
and EGL and not Wayland/DRI2/DRI3. In one of them (I think it's ES), the
default is to get an sRGB renderbuffer but either is possible with both
independent of how the image comes in. We *do* see it on DRI3 and Wayland
which is why this patch exists in the first place.

Post by Jason Ekstrand
So no, not for pretty much any externally-visible images AFAICT. Even
if it were true for scanout, the client would need to tell KMS, so KMS
could send a HDMI infoframe telling the display.

But scanout always does sRGB. If you want real UNORM, then you'll have to
add kernel API.

Post by Jason Ekstrand
Colourspaces \_o_/

Post by Jason Ekstrand
As for enums, sure, that can probably happen. GL and ISL both have enums
for colorspace that we could re-use.

Yes, having too few format tokens is not a problem we have. We seem to
have about as many of those as we have things called 'DRI2'.

Heh

[Jason Ekstrand]

Post by Jason Ekstrand

Post by Jason Ekstrand
Hi,

Post by Jason Ekstrand

Post by Daniel Stone

Post by Jason Ekstrand
The long answer is that the DRI formats do not specify a colorspace.

Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
equivalent to the latter, bar the addition of a special and unique
SARGB8 token, i.e. ARGB8888 with the sRGB transfer function (and
presumably primaries?). The rest are presumed UNORM.

Wha? What's the difference between SARGB8 and ARGB8888 then? My
understanding was that scanout basically treats everything as sRGB

anyway.

Post by Jason Ekstrand
Clearly, my sRGB knowledge is imperfect.

GBM_FORMAT_ARGB8888 (aka DRI_IMAGE_FOURCC_ARGB8888), gets mapped to
DRI_IMAGE_FORMAT_ARGB8888, which gets mapped to
MESA_FORMAT_B8G8R8X8_UNORM (dri_util.c). Only
DRI_IMAGE_{FORMAT,FOURCC}_SARGB8 (no defined GBM token, but you can
pass it through the GBM API and it'll work sometimes) gets mapped to a
MESA_FORMAT_*_SRGB. So AFAICT, to get an sRGB scanout buffer from
Mesa/GBM, you'd need to allocate UNORM and do inverse-gamma in your
frag shader.
Wayland similarly never maps anything to sRGB.
X11 always imports EGLImages as UNORM, so blending would be broken in
a composited environment if we were actually allocating sRGB.

Blending *is* broken. I had a long chat with Owen Taylor about this some
time ago. Everything comes into X11 sRGB encoded and scanout treats it's
buffer as sRGB. X11 then stomps everything to UNORM and blends in the
wrong colorspace.

Post by Jason Ekstrand
i965 tries pretty hard to allocate sRGB images in the pre-DRIImage,
DRI2 (as in the X11 protocol named 'DRI2') codepath, but this isn't
used by Wayland, GBM, or DRI3.

Except that whether you get an sRGB renderbuffer or not is governed by GLX
and EGL and not Wayland/DRI2/DRI3. In one of them (I think it's ES), the
default is to get an sRGB renderbuffer but either is possible with both
independent of how the image comes in. We *do* see it on DRI3 and Wayland
which is why this patch exists in the first place.

Inserting some asserts and running through CI confirms this. There are
piles of times when we take a nominally UNORM DRI format and interpret it
as sRGB.

Post by Jason Ekstrand
So no, not for pretty much any externally-visible images AFAICT. Even

Post by Jason Ekstrand
if it were true for scanout, the client would need to tell KMS, so KMS
could send a HDMI infoframe telling the display.

But scanout always does sRGB. If you want real UNORM, then you'll have to
add kernel API.

Post by Jason Ekstrand
Colourspaces \_o_/

Post by Jason Ekstrand
As for enums, sure, that can probably happen. GL and ISL both have

enums

Post by Jason Ekstrand
for colorspace that we could re-use.

Yes, having too few format tokens is not a problem we have. We seem to
have about as many of those as we have things called 'DRI2'.

Heh

[Daniel Stone]

Hi,

Post by Jason Ekstrand

Post by Daniel Stone
i965 tries pretty hard to allocate sRGB images in the pre-DRIImage,
DRI2 (as in the X11 protocol named 'DRI2') codepath, but this isn't
used by Wayland, GBM, or DRI3.

Except that whether you get an sRGB renderbuffer or not is governed by GLX
and EGL and not Wayland/DRI2/DRI3. In one of them (I think it's ES), the
default is to get an sRGB renderbuffer but either is possible with both
independent of how the image comes in. We *do* see it on DRI3 and Wayland
which is why this patch exists in the first place.

Well, that's fairly depressing. So I guess SARGB8 is only used for
GLX_ARB_framebuffer_sRGB, and the rest is just magically transforming
(ostensibly) _UNORM Mesa formats into _SRGB?

intel_gles3_srgb_workaround() is ... quite a thing.

Post by Jason Ekstrand

Post by Daniel Stone
So no, not for pretty much any externally-visible images AFAICT. Even
if it were true for scanout, the client would need to tell KMS, so KMS
could send a HDMI infoframe telling the display.

But scanout always does sRGB. If you want real UNORM, then you'll have to
add kernel API.

I'm kinda confused on this point; the colour transform matrix set up
by default is an identity mapping, rather than a degamma-to-linear
(ignoring the 16-235 vs. limited dance ...). In theory, if we're
sending sRGB, we should inform the sink via an AVI infoframe, but I
can't see anywhere we actually do that.

Anyway, I don't see this patch making the historical mistake any
better or worse, so let's just mentally file it away to bottom out one
day and move on.

Cheers,
Daniel

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_screen.c | 51 ++++++++++++++++++--------------
1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 3cf10b8..e5acd31 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -37,6 +37,7 @@
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
#include "brw_defines.h"
+#include "brw_state.h"
#include "compiler/nir/nir.h"

#include "utils.h"
@@ -318,19 +319,6 @@ modifier_is_supported(uint64_t modifier)
return false;
}

-static uint32_t
-modifier_to_tiling(uint64_t modifier)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
- if (tiling_modifier_map[i].modifier == modifier)
- return tiling_modifier_map[i].tiling;
- }
-
- unreachable("modifier_to_tiling should only receive known modifiers");
-}
-
static uint64_t
tiling_to_modifier(uint32_t tiling)
{
@@ -638,10 +626,8 @@ intel_create_image_common(__DRIscreen *dri_screen,
{
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
- uint32_t tiling;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
- unsigned tiled_height;
- int cpp;
+ bool ok;

/* Callers of this may specify a modifier, or a dri usage, but not both. The
* newer modifier interface deprecates the older usage flags newer modifier
@@ -671,23 +657,44 @@ intel_create_image_common(__DRIscreen *dri_screen,
modifier = I915_FORMAT_MOD_X_TILED;
}
}
- tiling = modifier_to_tiling(modifier);
- tiled_height = get_tiled_height(modifier, height);

image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
return NULL;

- cpp = _mesa_get_format_bytes(image->format);
- image->bo = brw_bo_alloc_tiled_2d(screen->bufmgr, "image",
- width, tiled_height, cpp, tiling,
- &image->pitch, 0);
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(modifier);
+
+ struct isl_surf surf;
+ ok = isl_surf_init(&screen->isl_dev, &surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = brw_isl_format_for_mesa_format(image->format),
+ .width = width,
+ .height = height,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = 1,
+ .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_STORAGE_BIT,
+ .tiling_flags = (1 << mod_info->tiling));
+ assert(ok);
+ if (!ok) {
+ free(image);
+ return NULL;
+ }
+
+ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+ isl_tiling_to_i915_tiling(mod_info->tiling),
+ surf.row_pitch, 0);
if (image->bo == NULL) {
free(image);
return NULL;
}
image->width = width;
image->height = height;
+ image->pitch = surf.row_pitch;
image->modifier = modifier;

return image;

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_screen.c | 51 ++++++++++++++++++--------------
1 file changed, 29 insertions(+), 22 deletions(-)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_screen.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index e5acd31..a896bc4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -857,8 +857,8 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
- unsigned tiled_height;
int i, index;
+ bool ok;

if (fds == NULL || num_fds < 1)
return NULL;
@@ -909,7 +909,6 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
image->modifier = modifier;
else
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
- tiled_height = get_tiled_height(image->modifier, height);

int size = 0;
for (i = 0; i < f->nplanes; i++) {
@@ -917,8 +916,33 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
image->offsets[index] = offsets[index];
image->strides[index] = strides[index];

- const int plane_height = tiled_height >> f->planes[i].height_shift;
- const int end = offsets[index] + plane_height * strides[index];
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
+ mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
+
+ struct isl_surf surf;
+ ok = isl_surf_init(&screen->isl_dev, &surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = brw_isl_format_for_mesa_format(format),
+ .width = image->width >> f->planes[i].width_shift,
+ .height = image->height >> f->planes[i].height_shift,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = 1,
+ .row_pitch = strides[index],
+ .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_STORAGE_BIT,
+ .tiling_flags = (1 << mod_info->tiling));
+ if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ const int end = offsets[index] + surf.size;
if (size < end)
size = end;
}

[Chad Versace]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_screen.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)

This patch adds more code, but it's code I trust.
Reviewed-by: Chad Versace <***@chromium.org>

[Rainer Hochecker]

This seems to breaks exporting 16bit vaapi images via drm buffers

[Jason Ekstrand]

Post by Rainer Hochecker
This seems to breaks exporting 16bit vaapi images via drm buffers

Yes, I'm aware of the problem and there are two patches on the list which
should fix it:

https://patchwork.freedesktop.org/patch/170051/
https://patchwork.freedesktop.org/patch/170052/

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

v2: Rename modifier to be more smart (Jason)

FINISHME: Use the kernel's final choice for the fb modifier

***@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
Write bandwidth: 615.28 MiB/s
***@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ytile
Read bandwidth: 571.13 MiB/s
Write bandwidth: 555.51 MiB/s
***@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ccs
Read bandwidth: 259.34 MiB/s
Write bandwidth: 337.83 MiB/s

v2: Move all references to the new fourcc code(s) to this patch.
v3: Rebase, remove Yf_CCS (Daniel)

Cc: Jason Ekstrand <***@jlekstrand.net>
Signed-off-by: Ben Widawsky <***@bwidawsk.net>
Acked-by: Daniel Stone <***@collabora.com>
---
src/mesa/drivers/dri/i965/intel_screen.c | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 6237931f..7307aae 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -51,6 +51,10 @@
#define DRM_FORMAT_MOD_LINEAR 0
#endif

+#ifndef I915_FORMAT_MOD_Y_TILED_CCS
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#endif
+
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
@@ -303,6 +307,8 @@ static const struct {
.since_gen = 1 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
.since_gen = 6 },
+ { .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
+ .since_gen = 9 },
};

static bool
@@ -566,6 +572,7 @@ enum modifier_priority {
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
+ MODIFIER_PRIORITY_Y_CCS,
};

const uint64_t priority_to_modifier[] = {
@@ -573,6 +580,7 @@ const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+ [MODIFIER_PRIORITY_Y_CCS] = /* I915_FORMAT_MOD_Y_TILED_CCS */ fourcc_mod_code(INTEL, 4),
};

static uint64_t
@@ -584,6 +592,9 @@ select_best_modifier(struct gen_device_info *devinfo,

for (int i = 0; i < count; i++) {
switch (modifiers[i]) {
+ case /* I915_FORMAT_MOD_Y_TILED_CCS */ fourcc_mod_code(INTEL, 4):
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
+ break;
case I915_FORMAT_MOD_Y_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_Y);
break;

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.

Primarily this patch is split out for review, it can be squashed in
later if preferred.

v2:
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release

v3:
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.

v4:
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)

v5 (Jason Ekstrand):
- Base the decision to allocate a CCS on the image modifier

Signed-off-by: Ben Widawsky <***@bwidawsk.net>
Acked-by: Daniel Stone <***@collabora.com>
Reviewed-by: Topi Pohjolainen <***@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 123 +++++++++++++++++++++++---
1 file changed, 113 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e3de386..608317a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,6 +59,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLuint num_samples);

+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ int init_value);
+
/**
* Determine which MSAA layout should be used by the MSAA surface being
* created, based on the chip generation and the surface type.
@@ -886,27 +891,99 @@ miptree_create_for_planar_image(struct brw_context *brw,
return planar_mt;
}

+static bool
+create_ccs_buf_for_image(struct brw_context *brw,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt,
+ enum isl_aux_state initial_state)
+{
+ struct isl_surf temp_main_surf, temp_ccs_surf;
+
+ /* There isn't anything specifically wrong with there being an offset, in
+ * which case, the CCS miptree's offset should be mt->offset +
+ * image->aux_offset. However, the code today only will have an offset when
+ * this miptree is pointing to a slice from another miptree, and in that case
+ * we'd need to offset within the AUX CCS buffer properly. It's questionable
+ * whether our code handles that case properly, and since it can never happen
+ * for scanout, just use the assertion to prevent it.
+ */
+ assert(mt->offset == 0);
+
+ /* CCS is only supported for very simple miptrees */
+ assert(image->aux_offset && image->aux_pitch);
+ assert(image->tile_x == 0 && image->tile_y == 0);
+ assert(mt->num_samples <= 1);
+ assert(mt->first_level == 0);
+ assert(mt->last_level == 0);
+ assert(mt->logical_depth0 == 1);
+
+ /* We shouldn't already have a CCS */
+ assert(!mt->mcs_buf);
+
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ return false;
+
+ assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+ assert(temp_ccs_surf.row_pitch <= image->aux_pitch);
+
+ mt->mcs_buf = calloc(sizeof(*mt->mcs_buf), 1);
+ if (mt->mcs_buf == NULL)
+ return false;
+
+ mt->aux_state = create_aux_state_map(mt, initial_state);
+ if (!mt->aux_state) {
+ free(mt->mcs_buf);
+ mt->mcs_buf = NULL;
+ return false;
+ }
+
+ mt->mcs_buf->bo = image->bo;
+ brw_bo_reference(image->bo);
+
+ mt->mcs_buf->offset = image->aux_offset;
+ mt->mcs_buf->size = image->bo->size - image->aux_offset;
+ mt->mcs_buf->pitch = image->aux_pitch;
+ mt->mcs_buf->qpitch = 0;
+
+ intel_miptree_init_mcs(brw, mt, 0);
+ mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+
+ return true;
+}
+
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
bool is_winsys_image)
{
+ uint32_t mt_layout_flags = 0;
+
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);

if (!brw->ctx.TextureFormatSupported[format])
return NULL;

+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
+ /* If this image comes in from a window system, then it may get promoted to
+ * scanout at any time so we need to set the flag accordingly.
+ */
+ if (is_winsys_image)
+ mt_layout_flags |= MIPTREE_LAYOUT_FOR_SCANOUT;
+
/* If this image comes in from a window system, we have different
* requirements than if it comes in via an EGL import operation. Window
* system images can use any form of auxiliary compression we wish because
* they get "flushed" before being handed off to the window system and we
- * have the opportunity to do resolves. Window system buffers also may be
- * used for scanout so we need to flag that appropriately.
+ * have the opportunity to do resolves.
*/
- const uint32_t mt_layout_flags =
- is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;
+ if (!is_winsys_image &&
+ (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE))
+ mt_layout_flags |= MIPTREE_LAYOUT_DISABLE_AUX;

/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
@@ -943,15 +1020,41 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}

- /* Since CCS_E can compress more than just clear color, we create the
- * CCS for it up-front. For CCS_D which only compresses clears, we
- * create the CCS on-demand when a clear occurs that wants one.
- */
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- if (!intel_miptree_alloc_ccs(brw, mt)) {
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mt->aux_usage = mod_info->aux_usage;
+ /* If we are a window system buffer, then we can support fast-clears
+ * even if the modifier doesn't support them by doing a partial resolve
+ * as part of the flush operation.
+ */
+ mt->supports_fast_clear =
+ is_winsys_image || mod_info->supports_clear_color;
+
+ /* We don't know the actual state of the surface when we get it but we
+ * can make a pretty good guess based on the modifier. What we do know
+ * for sure is that it isn't in the AUX_INVALID state, so we just assume
+ * a worst case of compression.
+ */
+ enum isl_aux_state initial_state =
+ mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
+ ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
+
+ if (!create_ccs_buf_for_image(brw, image, mt, initial_state)) {
intel_miptree_release(&mt);
return NULL;
}
+ } else if (mt->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
}

return mt;

[Pohjolainen, Topi]

Post by Jason Ekstrand
This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.
Primarily this patch is split out for review, it can be squashed in
later if preferred.
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)
- Base the decision to allocate a CCS on the image modifier
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 123 +++++++++++++++++++++++---
1 file changed, 113 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e3de386..608317a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,6 +59,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLuint num_samples);
+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ int init_value);
+
/**
* Determine which MSAA layout should be used by the MSAA surface being
* created, based on the chip generation and the surface type.
@@ -886,27 +891,99 @@ miptree_create_for_planar_image(struct brw_context *brw,
return planar_mt;
}
+static bool
+create_ccs_buf_for_image(struct brw_context *brw,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt,
+ enum isl_aux_state initial_state)
+{
+ struct isl_surf temp_main_surf, temp_ccs_surf;
+
+ /* There isn't anything specifically wrong with there being an offset, in
+ * which case, the CCS miptree's offset should be mt->offset +
+ * image->aux_offset. However, the code today only will have an offset when
+ * this miptree is pointing to a slice from another miptree, and in that case
+ * we'd need to offset within the AUX CCS buffer properly. It's questionable
+ * whether our code handles that case properly, and since it can never happen
+ * for scanout, just use the assertion to prevent it.
+ */
+ assert(mt->offset == 0);
+
+ /* CCS is only supported for very simple miptrees */
+ assert(image->aux_offset && image->aux_pitch);
+ assert(image->tile_x == 0 && image->tile_y == 0);
+ assert(mt->num_samples <= 1);
+ assert(mt->first_level == 0);
+ assert(mt->last_level == 0);
+ assert(mt->logical_depth0 == 1);
+
+ /* We shouldn't already have a CCS */
+ assert(!mt->mcs_buf);
+
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ return false;
+
+ assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+ assert(temp_ccs_surf.row_pitch <= image->aux_pitch);
+
+ mt->mcs_buf = calloc(sizeof(*mt->mcs_buf), 1);
+ if (mt->mcs_buf == NULL)
+ return false;
+
+ mt->aux_state = create_aux_state_map(mt, initial_state);
+ if (!mt->aux_state) {
+ free(mt->mcs_buf);
+ mt->mcs_buf = NULL;
+ return false;
+ }
+
+ mt->mcs_buf->bo = image->bo;
+ brw_bo_reference(image->bo);
+
+ mt->mcs_buf->offset = image->aux_offset;
+ mt->mcs_buf->size = image->bo->size - image->aux_offset;
+ mt->mcs_buf->pitch = image->aux_pitch;

I wonder if it would be more correct to use temp_ccs_surf.size and
temp_ccs_surf.row_pitch instead?

Post by Jason Ekstrand
+ mt->mcs_buf->qpitch = 0;
+
+ intel_miptree_init_mcs(brw, mt, 0);
+ mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+
+ return true;
+}
+
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
bool is_winsys_image)
{
+ uint32_t mt_layout_flags = 0;
+
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
if (!brw->ctx.TextureFormatSupported[format])
return NULL;
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
+ /* If this image comes in from a window system, then it may get promoted to
+ * scanout at any time so we need to set the flag accordingly.
+ */
+ if (is_winsys_image)
+ mt_layout_flags |= MIPTREE_LAYOUT_FOR_SCANOUT;
+
/* If this image comes in from a window system, we have different
* requirements than if it comes in via an EGL import operation. Window
* system images can use any form of auxiliary compression we wish because
* they get "flushed" before being handed off to the window system and we
- * have the opportunity to do resolves. Window system buffers also may be
- * used for scanout so we need to flag that appropriately.
+ * have the opportunity to do resolves.
*/
- const uint32_t mt_layout_flags =
- is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;
+ if (!is_winsys_image &&
+ (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE))
+ mt_layout_flags |= MIPTREE_LAYOUT_DISABLE_AUX;
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
@@ -943,15 +1020,41 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}
- /* Since CCS_E can compress more than just clear color, we create the
- * CCS for it up-front. For CCS_D which only compresses clears, we
- * create the CCS on-demand when a clear occurs that wants one.
- */
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- if (!intel_miptree_alloc_ccs(brw, mt)) {
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mt->aux_usage = mod_info->aux_usage;
+ /* If we are a window system buffer, then we can support fast-clears
+ * even if the modifier doesn't support them by doing a partial resolve
+ * as part of the flush operation.
+ */
+ mt->supports_fast_clear =
+ is_winsys_image || mod_info->supports_clear_color;
+
+ /* We don't know the actual state of the surface when we get it but we
+ * can make a pretty good guess based on the modifier. What we do know
+ * for sure is that it isn't in the AUX_INVALID state, so we just assume
+ * a worst case of compression.
+ */
+ enum isl_aux_state initial_state =
+ ISL_AUX_STATE_COMPRESSED_NO_CLEAR;

How do we know aux contains meaningful data?

Post by Jason Ekstrand
+
+ if (!create_ccs_buf_for_image(brw, image, mt, initial_state)) {
intel_miptree_release(&mt);
return NULL;
}
+ } else if (mt->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
}
return mt;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Pohjolainen, Topi]

Post by Pohjolainen, Topi

Post by Jason Ekstrand
This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.
Primarily this patch is split out for review, it can be squashed in
later if preferred.
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)
- Base the decision to allocate a CCS on the image modifier
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 123 +++++++++++++++++++++++---
1 file changed, 113 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e3de386..608317a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,6 +59,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLuint num_samples);
+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ int init_value);
+
/**
* Determine which MSAA layout should be used by the MSAA surface being
* created, based on the chip generation and the surface type.
@@ -886,27 +891,99 @@ miptree_create_for_planar_image(struct brw_context *brw,
return planar_mt;
}
+static bool
+create_ccs_buf_for_image(struct brw_context *brw,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt,
+ enum isl_aux_state initial_state)
+{
+ struct isl_surf temp_main_surf, temp_ccs_surf;
+
+ /* There isn't anything specifically wrong with there being an offset, in
+ * which case, the CCS miptree's offset should be mt->offset +
+ * image->aux_offset. However, the code today only will have an offset when
+ * this miptree is pointing to a slice from another miptree, and in that case
+ * we'd need to offset within the AUX CCS buffer properly. It's questionable
+ * whether our code handles that case properly, and since it can never happen
+ * for scanout, just use the assertion to prevent it.
+ */
+ assert(mt->offset == 0);
+
+ /* CCS is only supported for very simple miptrees */
+ assert(image->aux_offset && image->aux_pitch);
+ assert(image->tile_x == 0 && image->tile_y == 0);
+ assert(mt->num_samples <= 1);
+ assert(mt->first_level == 0);
+ assert(mt->last_level == 0);
+ assert(mt->logical_depth0 == 1);
+
+ /* We shouldn't already have a CCS */
+ assert(!mt->mcs_buf);
+
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ return false;
+
+ assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+ assert(temp_ccs_surf.row_pitch <= image->aux_pitch);
+
+ mt->mcs_buf = calloc(sizeof(*mt->mcs_buf), 1);
+ if (mt->mcs_buf == NULL)
+ return false;
+
+ mt->aux_state = create_aux_state_map(mt, initial_state);
+ if (!mt->aux_state) {
+ free(mt->mcs_buf);
+ mt->mcs_buf = NULL;
+ return false;
+ }
+
+ mt->mcs_buf->bo = image->bo;
+ brw_bo_reference(image->bo);
+
+ mt->mcs_buf->offset = image->aux_offset;
+ mt->mcs_buf->size = image->bo->size - image->aux_offset;
+ mt->mcs_buf->pitch = image->aux_pitch;

I wonder if it would be more correct to use temp_ccs_surf.size and
temp_ccs_surf.row_pitch instead?

And again, I started reading the next patch and it made me think this again.
Of course they need to be the given values. So ignore the comment.

Post by Pohjolainen, Topi

Post by Jason Ekstrand
+ mt->mcs_buf->qpitch = 0;
+
+ intel_miptree_init_mcs(brw, mt, 0);
+ mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+
+ return true;
+}
+
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
bool is_winsys_image)
{
+ uint32_t mt_layout_flags = 0;
+
if (image->planar_format && image->planar_format->nplanes > 0)
return miptree_create_for_planar_image(brw, image, target);
if (!brw->ctx.TextureFormatSupported[format])
return NULL;
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
+ /* If this image comes in from a window system, then it may get promoted to
+ * scanout at any time so we need to set the flag accordingly.
+ */
+ if (is_winsys_image)
+ mt_layout_flags |= MIPTREE_LAYOUT_FOR_SCANOUT;
+
/* If this image comes in from a window system, we have different
* requirements than if it comes in via an EGL import operation. Window
* system images can use any form of auxiliary compression we wish because
* they get "flushed" before being handed off to the window system and we
- * have the opportunity to do resolves. Window system buffers also may be
- * used for scanout so we need to flag that appropriately.
+ * have the opportunity to do resolves.
*/
- const uint32_t mt_layout_flags =
- is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : MIPTREE_LAYOUT_DISABLE_AUX;
+ if (!is_winsys_image &&
+ (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE))
+ mt_layout_flags |= MIPTREE_LAYOUT_DISABLE_AUX;
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
@@ -943,15 +1020,41 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
}
}
- /* Since CCS_E can compress more than just clear color, we create the
- * CCS for it up-front. For CCS_D which only compresses clears, we
- * create the CCS on-demand when a clear occurs that wants one.
- */
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- if (!intel_miptree_alloc_ccs(brw, mt)) {
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mt->aux_usage = mod_info->aux_usage;
+ /* If we are a window system buffer, then we can support fast-clears
+ * even if the modifier doesn't support them by doing a partial resolve
+ * as part of the flush operation.
+ */
+ mt->supports_fast_clear =
+ is_winsys_image || mod_info->supports_clear_color;
+
+ /* We don't know the actual state of the surface when we get it but we
+ * can make a pretty good guess based on the modifier. What we do know
+ * for sure is that it isn't in the AUX_INVALID state, so we just assume
+ * a worst case of compression.
+ */
+ enum isl_aux_state initial_state =
+ ISL_AUX_STATE_COMPRESSED_NO_CLEAR;

How do we know aux contains meaningful data?

Post by Jason Ekstrand
+
+ if (!create_ccs_buf_for_image(brw, image, mt, initial_state)) {
intel_miptree_release(&mt);
return NULL;
}
+ } else if (mt->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
}
return mt;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)

v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)

v4 (Jason Ekstrand):
Use the aux_pitch in the image instead of calculating it

Cc: Jason Ekstrand <***@jlekstrand.net>
Signed-off-by: Ben Widawsky <***@bwidawsk.net>
Acked-by: Daniel Stone <***@collabora.com>
---
src/mesa/drivers/dri/i965/intel_screen.c | 54 +++++++++++++++++++-------------
1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 7d6adb7..6237931f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -757,7 +757,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
case __DRI_IMAGE_ATTRIB_FOURCC:
return intel_lookup_fourcc(image->dri_format, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
- *value = 1;
+ *value = image->aux_offset ? 2: 1;
return true;
case __DRI_IMAGE_ATTRIB_OFFSET:
*value = image->offset;
@@ -1149,31 +1149,43 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
struct intel_image_format *f;
__DRIimage *image;

- if (parent == NULL || parent->planar_format == NULL)
- return NULL;
-
- f = parent->planar_format;
-
- if (plane >= f->nplanes)
- return NULL;
-
- width = parent->width >> f->planes[plane].width_shift;
- height = parent->height >> f->planes[plane].height_shift;
- dri_format = f->planes[plane].dri_format;
- index = f->planes[plane].buffer_index;
- offset = parent->offsets[index];
- stride = parent->strides[index];
+ if (parent == NULL) {
+ return NULL;
+ } else if (parent->planar_format == NULL) {
+ const bool is_aux = parent->aux_offset && plane == 1;
+ if (!is_aux)
+ return NULL;
+
+ width = parent->width;
+ height = parent->height;
+ dri_format = parent->dri_format;
+ offset = parent->aux_offset;
+ stride = parent->aux_pitch;
+ } else {
+ /* Planar formats don't support aux buffers/images */
+ assert(!parent->aux_offset);
+ f = parent->planar_format;
+
+ if (plane >= f->nplanes)
+ return NULL;
+
+ width = parent->width >> f->planes[plane].width_shift;
+ height = parent->height >> f->planes[plane].height_shift;
+ dri_format = f->planes[plane].dri_format;
+ index = f->planes[plane].buffer_index;
+ offset = parent->offsets[index];
+ stride = parent->strides[index];
+
+ if (offset + height * stride > parent->bo->size) {
+ _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
+ return NULL;
+ }
+ }

image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
if (image == NULL)
return NULL;

- if (offset + height * stride > parent->bo->size) {
- _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
- free(image);
- return NULL;
- }
-
image->bo = parent->bo;
brw_bo_reference(parent->bo);
image->modifier = parent->modifier;

[Pohjolainen, Topi]

Post by Jason Ekstrand
v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)
v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)
Use the aux_pitch in the image instead of calculating it
---
src/mesa/drivers/dri/i965/intel_screen.c | 54 +++++++++++++++++++-------------
1 file changed, 33 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 7d6adb7..6237931f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -757,7 +757,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
return intel_lookup_fourcc(image->dri_format, value);
- *value = 1;
+ *value = image->aux_offset ? 2: 1;

Missing space after '2'.

Post by Jason Ekstrand
return true;
*value = image->offset;
@@ -1149,31 +1149,43 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
struct intel_image_format *f;
__DRIimage *image;
- if (parent == NULL || parent->planar_format == NULL)
- return NULL;
-
- f = parent->planar_format;
-
- if (plane >= f->nplanes)
- return NULL;
-
- width = parent->width >> f->planes[plane].width_shift;
- height = parent->height >> f->planes[plane].height_shift;
- dri_format = f->planes[plane].dri_format;
- index = f->planes[plane].buffer_index;
- offset = parent->offsets[index];
- stride = parent->strides[index];
+ if (parent == NULL) {
+ return NULL;
+ } else if (parent->planar_format == NULL) {
+ const bool is_aux = parent->aux_offset && plane == 1;
+ if (!is_aux)
+ return NULL;
+
+ width = parent->width;
+ height = parent->height;
+ dri_format = parent->dri_format;
+ offset = parent->aux_offset;
+ stride = parent->aux_pitch;
+ } else {
+ /* Planar formats don't support aux buffers/images */
+ assert(!parent->aux_offset);
+ f = parent->planar_format;
+
+ if (plane >= f->nplanes)
+ return NULL;
+
+ width = parent->width >> f->planes[plane].width_shift;
+ height = parent->height >> f->planes[plane].height_shift;
+ dri_format = f->planes[plane].dri_format;
+ index = f->planes[plane].buffer_index;
+ offset = parent->offsets[index];
+ stride = parent->strides[index];
+
+ if (offset + height * stride > parent->bo->size) {
+ _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
+ return NULL;
+ }
+ }
image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
if (image == NULL)
return NULL;
- if (offset + height * stride > parent->bo->size) {
- _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
- free(image);
- return NULL;
- }
-
image->bo = parent->bo;
brw_bo_reference(parent->bo);
image->modifier = parent->modifier;
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

From: Ben Widawsky <***@bwidawsk.net>

Previously images did not support any auxiliary compression surfaces
(CCS, MCS, or HiZ). That's about to change. This patch just adds the
fields to __DRIimageRec to make auxiliary surfaces possible.

v2 (Jason Ekstrand):
- Add an aux_pitch parameter as well as aux_offset

Signed-off-by: Ben Widawsky <***@bwidawsk.net>
Acked-by: Daniel Stone <***@collabora.com>
---
src/mesa/drivers/dri/i965/intel_image.h | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_image.h b/src/mesa/drivers/dri/i965/intel_image.h
index cf06105..5ac5c31 100644
--- a/src/mesa/drivers/dri/i965/intel_image.h
+++ b/src/mesa/drivers/dri/i965/intel_image.h
@@ -92,6 +92,12 @@ struct __DRIimageRec {
/** The image was created with EGL_EXT_image_dma_buf_import. */
bool dma_buf_imported;

+ /** Offset of the auxiliary compression surface in the bo. */
+ uint32_t aux_offset;
+
+ /** Pitch of the auxiliary compression surface. */
+ uint32_t aux_pitch;
+
/**
* Provided by EGL_EXT_image_dma_buf_import.
* \{

[Jason Ekstrand]

It's no longer used.
---
src/mesa/drivers/dri/i965/intel_screen.c | 20 +++-----------------
1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index a896bc4..94787ff 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -296,14 +296,13 @@ static const struct {
uint32_t tiling;
uint64_t modifier;
unsigned since_gen;
- unsigned height_align;
} tiling_modifier_map[] = {
{ .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR,
- .since_gen = 1, .height_align = 1 },
+ .since_gen = 1 },
{ .tiling = I915_TILING_X, .modifier = I915_FORMAT_MOD_X_TILED,
- .since_gen = 1, .height_align = 8 },
+ .since_gen = 1 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
- .since_gen = 6, .height_align = 32 },
+ .since_gen = 6 },
};

static bool
@@ -332,19 +331,6 @@ tiling_to_modifier(uint32_t tiling)
unreachable("tiling_to_modifier received unknown tiling mode");
}

-static unsigned
-get_tiled_height(uint64_t modifier, unsigned height)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
- if (tiling_modifier_map[i].modifier == modifier)
- return ALIGN(height, tiling_modifier_map[i].height_align);
- }
-
- unreachable("get_tiled_height received unknown tiling mode");
-}
-
static void
intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
{

[Chad Versace]

Post by Jason Ekstrand
It's no longer used.

And the tree still builds.

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_screen.c | 20 +++-----------------
1 file changed, 3 insertions(+), 17 deletions(-)

[Jason Ekstrand]

---
src/intel/isl/isl_drm.c | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 1dc3da2..e2e873d 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -52,6 +52,10 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
}
}

+#ifndef I915_FORMAT_MOD_Y_TILED_CCS
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#endif
+
struct isl_drm_modifier_info modifier_info[] = {
{
.modifier = DRM_FORMAT_MOD_NONE,
@@ -68,6 +72,13 @@ struct isl_drm_modifier_info modifier_info[] = {
.name = "I915_FORMAT_MOD_Y_TILED",
.tiling = ISL_TILING_Y0,
},
+ {
+ .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
+ .name = "I915_FORMAT_MOD_Y_TILED_CCS",
+ .tiling = ISL_TILING_Y0,
+ .aux_usage = ISL_AUX_USAGE_CCS_E,
+ .supports_clear_color = false,
+ },
};

const struct isl_drm_modifier_info *

[Chad Versace]

Post by Jason Ekstrand
---
src/intel/isl/isl_drm.c | 11 +++++++++++
1 file changed, 11 insertions(+)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/intel/isl/isl.c | 4 +++-
src/intel/isl/isl.h | 3 ++-
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +++++---
4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 860fc28..f2ccb71 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1666,7 +1666,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
- struct isl_surf *ccs_surf)
+ struct isl_surf *ccs_surf,
+ uint32_t row_pitch)
{
assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(ISL_DEV_GEN(dev) >= 7);
@@ -1723,6 +1724,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
.levels = surf->levels,
.array_len = surf->logical_level0_px.array_len,
.samples = 1,
+ .row_pitch = row_pitch,
.usage = ISL_SURF_USAGE_CCS_BIT,
.tiling_flags = ISL_TILING_CCS_BIT);
}
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index dc3eada..40623e0 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1630,7 +1630,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
- struct isl_surf *ccs_surf);
+ struct isl_surf *ccs_surf,
+ uint32_t row_pitch /**< Ignored if 0 */);

#define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 9405a8c..d14ccff 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -211,7 +211,7 @@ make_surface(const struct anv_device *dev,
if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
assert(image->aux_surface.isl.size == 0);
ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
- &image->aux_surface.isl);
+ &image->aux_surface.isl, 0);
if (ok) {
add_surface(image, &image->aux_surface);

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 608317a..62a9e5f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -921,7 +921,8 @@ create_ccs_buf_for_image(struct brw_context *brw,
assert(!mt->mcs_buf);

intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
- if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf,
+ &temp_ccs_surf, 0))
return false;

assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
@@ -1794,7 +1795,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* calculate equivalent CCS surface against it.
*/
intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
- if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf,
+ &temp_ccs_surf, 0))
return false;

assert(temp_ccs_surf.size &&
@@ -3973,7 +3975,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
if (brw->gen >= 8)
assert(mt->halign == 16);

- isl_surf_get_ccs_surf(&brw->isl_dev, surf, surf);
+ isl_surf_get_ccs_surf(&brw->isl_dev, surf, surf, 0);
break;
}

[Chad Versace]

Post by Jason Ekstrand
---
src/intel/isl/isl.c | 4 +++-
src/intel/isl/isl.h | 3 ++-
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +++++---
4 files changed, 11 insertions(+), 6 deletions(-)

Reviewed-by: Chad Versace <***@chromium.org>

[Jason Ekstrand]

---
src/mesa/drivers/dri/i965/intel_screen.c | 55 +++++++++++++++++++++++++++++---
1 file changed, 50 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 94787ff..7d6adb7 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -671,7 +671,21 @@ intel_create_image_common(__DRIscreen *dri_screen,
return NULL;
}

- image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+ struct isl_surf aux_surf;
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0);
+ assert(ok);
+ if (!ok) {
+ free(image);
+ return NULL;
+ }
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ aux_surf.size = 0;
+ }
+
+ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
+ surf.size + aux_surf.size,
isl_tiling_to_i915_tiling(mod_info->tiling),
surf.row_pitch, 0);
if (image->bo == NULL) {
@@ -683,6 +697,11 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->pitch = surf.row_pitch;
image->modifier = modifier;

+ if (aux_surf.size) {
+ image->aux_offset = surf.size;
+ image->aux_pitch = aux_surf.row_pitch;
+ }
+
return image;
}

@@ -896,18 +915,18 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
else
image->modifier = tiling_to_modifier(image->bo->tiling_mode);

+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
int size = 0;
+ struct isl_surf surf;
for (i = 0; i < f->nplanes; i++) {
index = f->planes[i].buffer_index;
image->offsets[index] = offsets[index];
image->strides[index] = strides[index];

- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(image->modifier);
-
mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);

- struct isl_surf surf;
ok = isl_surf_init(&screen->isl_dev, &surf,
.dim = ISL_SURF_DIM_2D,
.format = brw_isl_format_for_mesa_format(format),
@@ -933,6 +952,32 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
size = end;
}

+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ /* Even though we initialize surf in the loop above, we know that
+ * anything with CCS_E will have exactly one plane so surf is properly
+ * initialized when we get here.
+ */
+ assert(f->nplanes == 1);
+
+ image->aux_offset = offsets[1];
+ image->aux_pitch = strides[1];
+
+ struct isl_surf aux_surf;
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
+ image->aux_pitch);
+ if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ const int end = image->aux_offset + surf.size;
+ if (size < end)
+ size = end;
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ }
+
/* Check that the requested image actually fits within the BO. 'size'
* is already relative to the offsets, so we don't need to add that. */
if (image->bo->size == 0) {

[Pohjolainen, Topi]

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_screen.c | 55 +++++++++++++++++++++++++++++---
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 94787ff..7d6adb7 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -671,7 +671,21 @@ intel_create_image_common(__DRIscreen *dri_screen,
return NULL;
}
- image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+ struct isl_surf aux_surf;
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0);
+ assert(ok);
+ if (!ok) {
+ free(image);
+ return NULL;
+ }
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ aux_surf.size = 0;
+ }
+
+ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
+ surf.size + aux_surf.size,
isl_tiling_to_i915_tiling(mod_info->tiling),
surf.row_pitch, 0);
if (image->bo == NULL) {
@@ -683,6 +697,11 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->pitch = surf.row_pitch;
image->modifier = modifier;
+ if (aux_surf.size) {
+ image->aux_offset = surf.size;
+ image->aux_pitch = aux_surf.row_pitch;
+ }
+
return image;
}
@@ -896,18 +915,18 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
else
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
int size = 0;
+ struct isl_surf surf;
for (i = 0; i < f->nplanes; i++) {
index = f->planes[i].buffer_index;
image->offsets[index] = offsets[index];
image->strides[index] = strides[index];
- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(image->modifier);
-
mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
- struct isl_surf surf;
ok = isl_surf_init(&screen->isl_dev, &surf,
.dim = ISL_SURF_DIM_2D,
.format = brw_isl_format_for_mesa_format(format),
@@ -933,6 +952,32 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
size = end;
}
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ /* Even though we initialize surf in the loop above, we know that
+ * anything with CCS_E will have exactly one plane so surf is properly
+ * initialized when we get here.
+ */
+ assert(f->nplanes == 1);
+
+ image->aux_offset = offsets[1];
+ image->aux_pitch = strides[1];
+
+ struct isl_surf aux_surf;
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
+ image->aux_pitch);
+ if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ const int end = image->aux_offset + surf.size;

Shouldn't we use 'aux_surf.size' instead of 'surf.size'?

Post by Jason Ekstrand
+ if (size < end)
+ size = end;
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ }
+
/* Check that the requested image actually fits within the BO. 'size'
* is already relative to the offsets, so we don't need to add that. */
if (image->bo->size == 0) {
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

On Mon, Jun 26, 2017 at 12:50 PM, Pohjolainen, Topi <

Post by Jason Ekstrand

Post by Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_screen.c | 55

+++++++++++++++++++++++++++++---

Post by Jason Ekstrand
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c

b/src/mesa/drivers/dri/i965/intel_screen.c

Post by Jason Ekstrand
index 94787ff..7d6adb7 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -671,7 +671,21 @@ intel_create_image_common(__DRIscreen *dri_screen,
return NULL;
}
- image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+ struct isl_surf aux_surf;
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,

0);

Post by Jason Ekstrand
+ assert(ok);
+ if (!ok) {
+ free(image);
+ return NULL;
+ }
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ aux_surf.size = 0;
+ }
+
+ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
+ surf.size + aux_surf.size,
isl_tiling_to_i915_tiling(mod_

info->tiling),

Post by Jason Ekstrand
surf.row_pitch, 0);
if (image->bo == NULL) {
@@ -683,6 +697,11 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->pitch = surf.row_pitch;
image->modifier = modifier;
+ if (aux_surf.size) {
+ image->aux_offset = surf.size;
+ image->aux_pitch = aux_surf.row_pitch;
+ }
+
return image;
}
@@ -896,18 +915,18 @@ intel_create_image_from_fds_common(__DRIscreen

*dri_screen,

Post by Jason Ekstrand
else
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
int size = 0;
+ struct isl_surf surf;
for (i = 0; i < f->nplanes; i++) {
index = f->planes[i].buffer_index;
image->offsets[index] = offsets[index];
image->strides[index] = strides[index];
- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(image->modifier);
-
mesa_format format = driImageFormatToGLFormat(f->

planes[i].dri_format);

Post by Jason Ekstrand
- struct isl_surf surf;
ok = isl_surf_init(&screen->isl_dev, &surf,
.dim = ISL_SURF_DIM_2D,
.format = brw_isl_format_for_mesa_

format(format),

Post by Jason Ekstrand
@@ -933,6 +952,32 @@ intel_create_image_from_fds_common(__DRIscreen

*dri_screen,

Post by Jason Ekstrand
size = end;
}
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ /* Even though we initialize surf in the loop above, we know that
+ * anything with CCS_E will have exactly one plane so surf is

properly

Post by Jason Ekstrand
+ * initialized when we get here.
+ */
+ assert(f->nplanes == 1);
+
+ image->aux_offset = offsets[1];
+ image->aux_pitch = strides[1];
+
+ struct isl_surf aux_surf;
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
+ image->aux_pitch);
+ if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ const int end = image->aux_offset + surf.size;

Shouldn't we use 'aux_surf.size' instead of 'surf.size'?

Yes. Fixed locally.

Post by Jason Ekstrand

Post by Jason Ekstrand
+ if (size < end)
+ size = end;
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ }
+
/* Check that the requested image actually fits within the BO. 'size'
* is already relative to the offsets, so we don't need to add that.

*/

Post by Jason Ekstrand
if (image->bo->size == 0) {
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

Instead of always doing a full resolve, only resolve the bits that are
needed. This means that we only do a partial resolve when the miptree
modifier is I915_FORMAT_MOD_Y_TILED_CCS.
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37 +++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 +++++++
3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 15d66ee..5b13c66 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1324,7 +1324,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb->mt->num_samples <= 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
- intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
+ intel_miptree_prepare_external(brw, rb->mt);
} else {
intel_renderbuffer_downsample(brw, rb);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 62a9e5f..6fde981 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -48,6 +48,10 @@

#define FILE_DEBUG_FLAG DEBUG_MIPTREE

+#ifndef DRM_FORMAT_MOD_INVALID
+#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
+#endif
+
static void *intel_miptree_map_raw(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLbitfield mode);
@@ -344,6 +348,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->drm_modifier = DRM_FORMAT_MOD_INVALID;
mt->aux_usage = ISL_AUX_USAGE_NONE;
mt->supports_fast_clear = false;
mt->aux_state = NULL;
@@ -888,6 +893,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
planar_mt->plane[i - 1] = mt;
}

+ planar_mt->drm_modifier = image->modifier;
+
return planar_mt;
}

@@ -1005,6 +1012,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
mt->level[0].slice[0].y_offset = image->tile_y;
mt->total_width += image->tile_x;
mt->total_height += image->tile_y;
+ mt->drm_modifier = image->modifier;

/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
@@ -2828,6 +2836,35 @@ intel_miptree_finish_depth(struct brw_context *brw,
}
}

+void
+intel_miptree_prepare_external(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ bool supports_aux = false, supports_fast_clear = false;
+
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(mt->drm_modifier);
+
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* CCS_E is the only supported aux for external images and it's only
+ * supported on very simple images.
+ */
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+ assert(_mesa_is_format_color_format(mt->format));
+ assert(mt->first_level == mt->last_level);
+ assert(mt->logical_depth0 == 1);
+ assert(mt->num_samples <= 1);
+ assert(mt->mcs_buf != NULL);
+
+ supports_aux = true;
+ supports_fast_clear = mod_info->supports_clear_color;
+ }
+
+ intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+ 0, INTEL_REMAINING_LAYERS,
+ supports_aux, supports_fast_clear);
+}
+
/**
* Make it possible to share the BO backing the given miptree with another
* process or another miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2a4cda2..8dd3a5d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -646,6 +646,12 @@ struct intel_mipmap_tree
*/
bool is_scanout;

+ /**
+ * For external surfaces, this is DRM format modifier that was used to
+ * create or import the surface.
+ */
+ uint64_t drm_modifier;
+
/* These are also refcounted:
*/
GLuint refcount;
@@ -970,6 +976,9 @@ intel_miptree_finish_depth(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
bool depth_written);
+void
+intel_miptree_prepare_external(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);

void
intel_miptree_make_shareable(struct brw_context *brw,

[Eero Tamminen]

Hi,

I run this on few GEN9 machines and SynMark v7 DeferredAA test improved
~3%, so it seems multisample fast-clears do help. :-)


- Eero

Post by Jason Ekstrand
This series is a rework of Ben's series to enable the CCS format modifier.
It started as an attempt to rebase his original patches on top of my
resolve reworks inside the miptree code. However, as I started to dive
1) Thanks to the terrible set of INTEL_AUX_DISABLE_* flags that we use to
choose what aux buffers to use, we were set up to never use CCS_E for
any external buffers. Even when Y-tiled on gen9, the most they would
ever get was CCS_D.
2) Whether to do a full or partial resolve or not was based on is_scanout
and not on the actual modifier. If we use I915_FORMAT_MOD_Y_TILED (not
the CCS modifier) and choose to use CCS_E with it, it would only get
partial resolves and not full resolves. Of course, this wasn't
actually a problem thanks to problem 1 above.
3) If a user ever imported an image with I915_FORMAT_MOD_Y_TILED_CCS
through EGL or GBM and did glClear on it, they would get a fast clear
with no way to force a resolve before handing it off to the other
process. Since the other process doesn't know the clear color, this
means that any blocks in the clear state in the surface will get
whatever random clear color process B thinks it has.
4) There were three different places where we computed the pitch of the
CCS and they all did so differently. When we go to create the image,
we would allocate the CCS with the same pitch as the main surface. We
would then calculate the CCS pitch with ISL when we created mt->mcs_buf.
Finally, we had a different mechanism to compute the pitch when we pass
it back to the user. Fortunately, the first only caused us to over-
allocate and I think the last two were equivalent (at least for the
simple case) so nothing exploded.
5) Thanks again to our confusing aux enable/disable, we haven't been doing
multisample fast-clears since cec30a666930ddb8476a9452a89364a24979ff62
around a year ago.
This series takes a bit more round-about approach to enabling the CCS
* Patches 1-5 do a bit of refactoring and then rework the way we choose
the type of aux compression to use. They move us away from the crazy
enable/disable system to a simple choice system. This fixes (1) and (5)
above.
* Patches 6-15 refactor things so that we have only one path for going
from a __DRIimage to an intel_mipmap_tree. This was rather painful
because we have to be careful to take into account the differences
between window system images regular images.
* Patches 16-22 rework image creation and import to use ISL to do their
surface layout calculations. Previously, all of the surface layout
calculations were simply hand-rolled here. In the particular case of
images, the hand-rolling was fairly safe because they were only ever
simple 2D non-array images. However, with the addition of CCS, things
were going to get a bit tricky.
* Patches 23-30 add support for I915_FORMAT_MOD_Y_TILED.
I've tested this series on our Jenkins system which runs piglit as well as
the OpenGL and OpenGL ES test suites. Both piglit and the OpenGL ES suite
have some number of EGL tests which I hope have tested some of this. I've
also tested with kmscube and have verified that I get basically the same
bandwidth numbers as Ben got on his original series, so I think CCS is
working properly.
https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-ccs-mod
i965/miptree: Add a return for updating of winsys
i965/miptree: Allocate mt earlier in update winsys
i965: Support images with aux buffers
i965/miptree: Allocate mcs_buf for an image's CCS
i965: Pretend that CCS modified images are two planes
i965: Advertise the CCS modifier
i965/miptree: Delete the layered rendering resolve
i965/miptree: Rename the non_msrt_mcs functions to _ccs
i965: Don't bother with HiZ in renderbuffer_move_to_temp
i965: Clamp clear colors to the representable range
i965/miptree: Rework aux enabling
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
i965/miptree: Add tile_x/y to total_width/height
i965/miptree: Set level_x/h in create_for_dri_image
i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
i965/miptree: Add an explicit format parameter to create_for_dri_image
i965/miptree: Add support for window system images to
create_for_dri_image
i965: Use create_for_dri_image in intel_update_image_buffer
i965/miptree: Move CCS allocation into create_for_dri_image
i965: Add an isl_device to intel_screen
intel/isl: Add basic modifier introspection
intel/isl: Add a helper to convert tilings fro ISL to i915
i965/screen: Use ISL for allocating image BOs
i965/screen: Use ISL for doing image import checks
i965/screen: Drop get_tiled_height
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
i965/screen: Support import and export of surfaces with CCS
i965/miptree: More conservatively resolve external images
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.c | 4 +-
src/intel/isl/isl.h | 28 +-
src/intel/isl/isl_drm.c | 93 +++++
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 44 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++
src/mesa/drivers/dri/i965/intel_fbo.c | 30 +-
src/mesa/drivers/dri/i965/intel_image.h | 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 496 ++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 77 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 216 +++++++----
src/mesa/drivers/dri/i965/intel_screen.h | 4 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 98 +----
16 files changed, 767 insertions(+), 377 deletions(-)
create mode 100644 src/intel/isl/isl_drm.c

[Jason Ekstrand]

Post by Eero Tamminen
Hi,
I run this on few GEN9 machines and SynMark v7 DeferredAA test improved
~3%, so it seems multisample fast-clears do help. :-)

Thanks! I'll add that to the commit message on patch 5.

--Jason

Post by Eero Tamminen
- Eero

Post by Jason Ekstrand
This series is a rework of Ben's series to enable the CCS format modifier.
It started as an attempt to rebase his original patches on top of my
resolve reworks inside the miptree code. However, as I started to dive
1) Thanks to the terrible set of INTEL_AUX_DISABLE_* flags that we use to
choose what aux buffers to use, we were set up to never use CCS_E for
any external buffers. Even when Y-tiled on gen9, the most they would
ever get was CCS_D.
2) Whether to do a full or partial resolve or not was based on is_scanout
and not on the actual modifier. If we use I915_FORMAT_MOD_Y_TILED (not
the CCS modifier) and choose to use CCS_E with it, it would only get
partial resolves and not full resolves. Of course, this wasn't
actually a problem thanks to problem 1 above.
3) If a user ever imported an image with I915_FORMAT_MOD_Y_TILED_CCS
through EGL or GBM and did glClear on it, they would get a fast clear
with no way to force a resolve before handing it off to the other
process. Since the other process doesn't know the clear color, this
means that any blocks in the clear state in the surface will get
whatever random clear color process B thinks it has.
4) There were three different places where we computed the pitch of the
CCS and they all did so differently. When we go to create the image,
we would allocate the CCS with the same pitch as the main surface. We
would then calculate the CCS pitch with ISL when we created mt->mcs_buf.
Finally, we had a different mechanism to compute the pitch when we pass
it back to the user. Fortunately, the first only caused us to over-
allocate and I think the last two were equivalent (at least for the
simple case) so nothing exploded.
5) Thanks again to our confusing aux enable/disable, we haven't been doing
multisample fast-clears since cec30a666930ddb8476a9452a89364
a24979ff62
around a year ago.
This series takes a bit more round-about approach to enabling the CCS
* Patches 1-5 do a bit of refactoring and then rework the way we choose
the type of aux compression to use. They move us away from the crazy
enable/disable system to a simple choice system. This fixes (1) and (5)
above.
* Patches 6-15 refactor things so that we have only one path for going
from a __DRIimage to an intel_mipmap_tree. This was rather painful
because we have to be careful to take into account the differences
between window system images regular images.
* Patches 16-22 rework image creation and import to use ISL to do their
surface layout calculations. Previously, all of the surface layout
calculations were simply hand-rolled here. In the particular case of
images, the hand-rolling was fairly safe because they were only ever
simple 2D non-array images. However, with the addition of CCS, things
were going to get a bit tricky.
* Patches 23-30 add support for I915_FORMAT_MOD_Y_TILED.
I've tested this series on our Jenkins system which runs piglit as well as
the OpenGL and OpenGL ES test suites. Both piglit and the OpenGL ES suite
have some number of EGL tests which I hope have tested some of this. I've
also tested with kmscube and have verified that I get basically the same
bandwidth numbers as Ben got on his original series, so I think CCS is
working properly.
https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-ccs-mod
i965/miptree: Add a return for updating of winsys
i965/miptree: Allocate mt earlier in update winsys
i965: Support images with aux buffers
i965/miptree: Allocate mcs_buf for an image's CCS
i965: Pretend that CCS modified images are two planes
i965: Advertise the CCS modifier
i965/miptree: Delete the layered rendering resolve
i965/miptree: Rename the non_msrt_mcs functions to _ccs
i965: Don't bother with HiZ in renderbuffer_move_to_temp
i965: Clamp clear colors to the representable range
i965/miptree: Rework aux enabling
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
i965/miptree: Add tile_x/y to total_width/height
i965/miptree: Set level_x/h in create_for_dri_image
i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
i965/miptree: Add an explicit format parameter to create_for_dri_image
i965/miptree: Add support for window system images to
create_for_dri_image
i965: Use create_for_dri_image in intel_update_image_buffer
i965/miptree: Move CCS allocation into create_for_dri_image
i965: Add an isl_device to intel_screen
intel/isl: Add basic modifier introspection
intel/isl: Add a helper to convert tilings fro ISL to i915
i965/screen: Use ISL for allocating image BOs
i965/screen: Use ISL for doing image import checks
i965/screen: Drop get_tiled_height
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
i965/screen: Support import and export of surfaces with CCS
i965/miptree: More conservatively resolve external images
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.c | 4 +-
src/intel/isl/isl.h | 28 +-
src/intel/isl/isl_drm.c | 93 +++++
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 44 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++
src/mesa/drivers/dri/i965/intel_fbo.c | 30 +-
src/mesa/drivers/dri/i965/intel_image.h | 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 496
++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 77 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 216 +++++++----
src/mesa/drivers/dri/i965/intel_screen.h | 4 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 98 +----
16 files changed, 767 insertions(+), 377 deletions(-)
create mode 100644 src/intel/isl/isl_drm.c

_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Jason Ekstrand]

Post by Jason Ekstrand
This series is a rework of Ben's series to enable the CCS format modifier.
It started as an attempt to rebase his original patches on top of my
resolve reworks inside the miptree code. However, as I started to dive
1) Thanks to the terrible set of INTEL_AUX_DISABLE_* flags that we use to
choose what aux buffers to use, we were set up to never use CCS_E for
any external buffers. Even when Y-tiled on gen9, the most they would
ever get was CCS_D.
2) Whether to do a full or partial resolve or not was based on is_scanout
and not on the actual modifier. If we use I915_FORMAT_MOD_Y_TILED (not
the CCS modifier) and choose to use CCS_E with it, it would only get
partial resolves and not full resolves. Of course, this wasn't
actually a problem thanks to problem 1 above.
3) If a user ever imported an image with I915_FORMAT_MOD_Y_TILED_CCS
through EGL or GBM and did glClear on it, they would get a fast clear
with no way to force a resolve before handing it off to the other
process. Since the other process doesn't know the clear color, this
means that any blocks in the clear state in the surface will get
whatever random clear color process B thinks it has.
4) There were three different places where we computed the pitch of the
CCS and they all did so differently. When we go to create the image,
we would allocate the CCS with the same pitch as the main surface. We
would then calculate the CCS pitch with ISL when we created mt->mcs_buf.
Finally, we had a different mechanism to compute the pitch when we pass
it back to the user. Fortunately, the first only caused us to over-
allocate and I think the last two were equivalent (at least for the
simple case) so nothing exploded.
5) Thanks again to our confusing aux enable/disable, we haven't been doing
multisample fast-clears since cec30a666930ddb8476a9452a89364a24979ff62
around a year ago.
This series takes a bit more round-about approach to enabling the CCS
* Patches 1-5 do a bit of refactoring and then rework the way we choose
the type of aux compression to use. They move us away from the crazy
enable/disable system to a simple choice system. This fixes (1) and (5)
above.
* Patches 6-15 refactor things so that we have only one path for going
from a __DRIimage to an intel_mipmap_tree. This was rather painful
because we have to be careful to take into account the differences
between window system images regular images.
* Patches 16-22 rework image creation and import to use ISL to do their
surface layout calculations. Previously, all of the surface layout
calculations were simply hand-rolled here. In the particular case of
images, the hand-rolling was fairly safe because they were only ever
simple 2D non-array images. However, with the addition of CCS, things
were going to get a bit tricky.
* Patches 23-30 add support for I915_FORMAT_MOD_Y_TILED.
I've tested this series on our Jenkins system which runs piglit as well as
the OpenGL and OpenGL ES test suites. Both piglit and the OpenGL ES suite
have some number of EGL tests which I hope have tested some of this. I've
also tested with kmscube and have verified that I get basically the same
bandwidth numbers as Ben got on his original series, so I think CCS is
working properly.
https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-ccs-mod

I've rebased on top of Topi's ISL reworks and force-pushed that branch.
You can see the result of the rebase there.

Post by Jason Ekstrand
i965/miptree: Add a return for updating of winsys
i965/miptree: Allocate mt earlier in update winsys
i965: Support images with aux buffers
i965/miptree: Allocate mcs_buf for an image's CCS
i965: Pretend that CCS modified images are two planes
i965: Advertise the CCS modifier
i965/miptree: Delete the layered rendering resolve
i965/miptree: Rename the non_msrt_mcs functions to _ccs
i965: Don't bother with HiZ in renderbuffer_move_to_temp
i965: Clamp clear colors to the representable range
i965/miptree: Rework aux enabling
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
i965/miptree: Add tile_x/y to total_width/height
i965/miptree: Set level_x/h in create_for_dri_image
i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
i965/miptree: Add an explicit format parameter to create_for_dri_image
i965/miptree: Add support for window system images to
create_for_dri_image
i965: Use create_for_dri_image in intel_update_image_buffer
i965/miptree: Move CCS allocation into create_for_dri_image
i965: Add an isl_device to intel_screen
intel/isl: Add basic modifier introspection
intel/isl: Add a helper to convert tilings fro ISL to i915
i965/screen: Use ISL for allocating image BOs
i965/screen: Use ISL for doing image import checks
i965/screen: Drop get_tiled_height
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
i965/screen: Support import and export of surfaces with CCS
i965/miptree: More conservatively resolve external images
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.c | 4 +-
src/intel/isl/isl.h | 28 +-
src/intel/isl/isl_drm.c | 93 +++++
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 44 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++
src/mesa/drivers/dri/i965/intel_fbo.c | 30 +-
src/mesa/drivers/dri/i965/intel_image.h | 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 496
++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 77 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 216 +++++++----
src/mesa/drivers/dri/i965/intel_screen.h | 4 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 98 +----
16 files changed, 767 insertions(+), 377 deletions(-)
create mode 100644 src/intel/isl/isl_drm.c
--
2.5.0.400.gff86faf

[Pohjolainen, Topi]

Post by Jason Ekstrand

Post by Jason Ekstrand
This series is a rework of Ben's series to enable the CCS format modifier.
It started as an attempt to rebase his original patches on top of my
resolve reworks inside the miptree code. However, as I started to dive
1) Thanks to the terrible set of INTEL_AUX_DISABLE_* flags that we use to
choose what aux buffers to use, we were set up to never use CCS_E for
any external buffers. Even when Y-tiled on gen9, the most they would
ever get was CCS_D.
2) Whether to do a full or partial resolve or not was based on is_scanout
and not on the actual modifier. If we use I915_FORMAT_MOD_Y_TILED (not
the CCS modifier) and choose to use CCS_E with it, it would only get
partial resolves and not full resolves. Of course, this wasn't
actually a problem thanks to problem 1 above.
3) If a user ever imported an image with I915_FORMAT_MOD_Y_TILED_CCS
through EGL or GBM and did glClear on it, they would get a fast clear
with no way to force a resolve before handing it off to the other
process. Since the other process doesn't know the clear color, this
means that any blocks in the clear state in the surface will get
whatever random clear color process B thinks it has.
4) There were three different places where we computed the pitch of the
CCS and they all did so differently. When we go to create the image,
we would allocate the CCS with the same pitch as the main surface. We
would then calculate the CCS pitch with ISL when we created mt->mcs_buf.
Finally, we had a different mechanism to compute the pitch when we pass
it back to the user. Fortunately, the first only caused us to over-
allocate and I think the last two were equivalent (at least for the
simple case) so nothing exploded.
5) Thanks again to our confusing aux enable/disable, we haven't been doing
multisample fast-clears since cec30a666930ddb8476a9452a89364a24979ff62
around a year ago.
This series takes a bit more round-about approach to enabling the CCS
* Patches 1-5 do a bit of refactoring and then rework the way we choose
the type of aux compression to use. They move us away from the crazy
enable/disable system to a simple choice system. This fixes (1) and (5)
above.
* Patches 6-15 refactor things so that we have only one path for going
from a __DRIimage to an intel_mipmap_tree. This was rather painful
because we have to be careful to take into account the differences
between window system images regular images.
* Patches 16-22 rework image creation and import to use ISL to do their
surface layout calculations. Previously, all of the surface layout
calculations were simply hand-rolled here. In the particular case of
images, the hand-rolling was fairly safe because they were only ever
simple 2D non-array images. However, with the addition of CCS, things
were going to get a bit tricky.
* Patches 23-30 add support for I915_FORMAT_MOD_Y_TILED.

Suggestion to revise the commit message in patch 12.

Typo in the subject in patch 19.

In 25 there is a question about incoming aux data - it looks that were are
taking it as containing meaningful data in some cases.

Question in patch 27.

Typo in patch 28.

Post by Jason Ekstrand

Post by Jason Ekstrand
I've tested this series on our Jenkins system which runs piglit as well as
the OpenGL and OpenGL ES test suites. Both piglit and the OpenGL ES suite
have some number of EGL tests which I hope have tested some of this. I've
also tested with kmscube and have verified that I get basically the same
bandwidth numbers as Ben got on his original series, so I think CCS is
working properly.
https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-ccs-mod

I've rebased on top of Topi's ISL reworks and force-pushed that branch.
You can see the result of the rebase there.

Post by Jason Ekstrand
i965/miptree: Add a return for updating of winsys
i965/miptree: Allocate mt earlier in update winsys
i965: Support images with aux buffers
i965/miptree: Allocate mcs_buf for an image's CCS
i965: Pretend that CCS modified images are two planes
i965: Advertise the CCS modifier
i965/miptree: Delete the layered rendering resolve
i965/miptree: Rename the non_msrt_mcs functions to _ccs
i965: Don't bother with HiZ in renderbuffer_move_to_temp
i965: Clamp clear colors to the representable range
i965/miptree: Rework aux enabling
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
i965/miptree: Add tile_x/y to total_width/height
i965/miptree: Set level_x/h in create_for_dri_image
i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
i965/miptree: Add an explicit format parameter to create_for_dri_image
i965/miptree: Add support for window system images to
create_for_dri_image
i965: Use create_for_dri_image in intel_update_image_buffer
i965/miptree: Move CCS allocation into create_for_dri_image
i965: Add an isl_device to intel_screen
intel/isl: Add basic modifier introspection
intel/isl: Add a helper to convert tilings fro ISL to i915
i965/screen: Use ISL for allocating image BOs
i965/screen: Use ISL for doing image import checks
i965/screen: Drop get_tiled_height
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
i965/screen: Support import and export of surfaces with CCS
i965/miptree: More conservatively resolve external images
src/intel/Makefile.am | 1 +
src/intel/Makefile.sources | 1 +
src/intel/isl/isl.c | 4 +-
src/intel/isl/isl.h | 28 +-
src/intel/isl/isl_drm.c | 93 +++++
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 44 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 40 +++
src/mesa/drivers/dri/i965/intel_fbo.c | 30 +-
src/mesa/drivers/dri/i965/intel_image.h | 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 496
++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 77 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 216 +++++++----
src/mesa/drivers/dri/i965/intel_screen.h | 4 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 98 +----
16 files changed, 767 insertions(+), 377 deletions(-)
create mode 100644 src/intel/isl/isl_drm.c
--
2.5.0.400.gff86faf

_______________________________________________
mesa-dev mailing list
https://lists.freedesktop.org/mailman/listinfo/mesa-dev